NONVOLATILE NANOTUBE DIODES AND NONVOLATILE NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING SAME

• US 20080170429A1
• Filed: 08/08/2007
• Published: 07/17/2008
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: SIVARAJAN, Ramesh, RUECKES, Thomas, BERTIN, Claude L., KONSEK, Steven L., MEINHOLD, Mitchell, GHENCIU, Eliodor G., HUANG, X. M. H.
• Granted Patent: US 8,217,490 B2
• Time in Patent Office: Days
• US Class Current: 365/151
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.

Claims

1. A non-volatile nanotube switch, comprising:

a first conductive terminal;

a nanotube block comprising a multilayer nanotube fabric, at least a portion of the nanotube block being positioned over and in contact with at least a portion of the first conductive terminal;

a second conductive terminal, at least a portion of the second conductive terminal being positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second conductive terminals; and

control circuitry in electrical communication with and capable of applying electrical stimulus to the first and second conductive terminals,

wherein the nanotube block is capable of switching between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals, and

wherein, for each different electronic state of the plurality of electronic states, the nanotube block provides an electrical pathway of corresponding different resistance between the first and second conductive terminals.

2. The switch of claim 1, wherein substantially the entire nanotube block is positioned over substantially the entire first conductive terminal, and wherein substantially the entire second conductive terminal is positioned over substantially the entire nanotube block.

3. The switch of claim 2, wherein the first and second conductive terminals and the nanotube block each have a substantially circular lateral shape.

4. The switch of claim 2, wherein the first and second conductive terminals and the nanotube block each have a substantially rectangular lateral shape.

5. The switch of claim 2, wherein the first and second conductive terminals and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm.

6. The switch of claim 2, wherein the first and second conductive terminals and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm.

7. The switch of claim 2, wherein the first and second conductive terminals and the nanotube block each have lateral dimension of less than about 10 nm.

8. The switch of claim 1, wherein the nanotube block has a thickness between about 10 nm and about 200 nm.

9. The switch of claim 1, wherein the nanotube block has a thickness between about 10 nm and about 50 nm.

10. The switch of claim 1, wherein the control circuitry includes a diode in direct physical contact with the first conductive terminal.

11. The switch of claim 10, wherein the first conductive terminal is positioned over the diode.

12. The switch of claim 10, wherein the diode is positioned over the second conductive terminal.

13. The switch of claim 10, wherein the diode, the nanotube block, and the first and second conductive terminals have substantially the same lateral dimensions.

14. The switch of claim 10, wherein the diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor.

15. The switch of claim 10, wherein the diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon.

16. The switch of claim 1, wherein the control circuitry includes a semiconductor field effect transistor in contact with the first conductive terminal.

17. The switch of claim 1, wherein the first and second conductive terminals each comprise a conductive material independently selected from the group consisting of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, Pbin, TiW, RuN, RuO, TiN, TaN, CoSi_x, and TiSi_x.

18. The switch of claim 1, wherein the nanotube block further comprises a porous dielectric material.

19. The switch of claim 18, wherein the porous dielectric material comprises one of a spin-on glass and a spin-on low-K dielectric.

20. The switch of claim 1, wherein the nanotube block further comprises a nonporous dielectric material.

21. The switch of claim 20, wherein the nonporous dielectric material comprises hafnium oxide.

22. A high-density memory array, comprising:

a plurality of word lines and a plurality of bit lines;

a plurality of memory cells, each memory cell comprising;

a first conductive terminal;

a nanotube block over the first conductive terminal, the nanotube block comprising a multilayer nanotube fabric;

a second conductive terminal over the nanotube block and in electrical communication with a word line of the plurality of word lines; and

a diode in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals,

wherein the nanotube block has a thickness that defines a spacing between the first and second conductive terminals, and

wherein a logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.

23. The array of claim 22, wherein the diode is positioned under the first conductive terminal.

24. The array of claim 22, wherein the diode is positioned over the second conductive terminal.

25. The array of claim 22, wherein the diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions.

26. The array of claim 22, wherein the diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape.

27. The array of claim 22, wherein the diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape.

28. The array of claim 22, wherein the diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm.

29. The array of claim 28, wherein the memory cells are spaced from each other by between about 200 nm and about 22 nm.

30. The array of claim 22, wherein the diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm.

31. The array of claim 30, wherein the memory cells of the array are spaced from each other by between about 220 nm and about 10 nm.

32. The array of claim 22, wherein some memory cells of the array are laterally spaced relative to each other, and wherein other memory cells of the array are stacked on top of each other.

33. The array of claim 32, wherein some of the memory cells of the array that are stacked on top of each other share a bit line.

34. The array of claim 33, wherein some of the memory cells of the array that are laterally spaced relative to each other share a word line.

35. The array of claim 22, wherein the plurality of word lines are substantially perpendicular to the plurality of bit lines.

36. The array of claim 22, wherein the thickness of the nanotube block is between about 10 nm and about 200 nm.

37. The array of claim 22, wherein the thickness of the nanotube block is between about 10 nm and about 50 nm.

38. A high-density memory array, comprising:

a plurality of word lines and a plurality of bit lines;

a plurality of memory cells, each memory cell comprising;

a first conductive terminal;

a nanotube block over the first conductive terminal, the nanotube block comprising a multilayer nanotube fabric;

a second conductive terminal over the nanotube block and in electrical communication with a bit line of the plurality of bit lines; and

a diode in electrical communication with a word line of the plurality of word lines,

wherein the nanotube block has a thickness that defines a spacing between the first and second conductive terminals, and

wherein a logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.

39. The array of claim 38, wherein the diode is positioned under the first conductive terminal.

40. The array of claim 38, wherein the diode is positioned over the second conductive terminal.

41. The array of claim 38, wherein the diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions.

42. The array of claim 38, wherein the diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape.

43. The array of claim 38, wherein the diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape.

44. The array of claim 38, wherein the diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm.

45. The array of claim 38, wherein the memory cells are spaced from each other by between about 200 nm and about 22 nm.

46. The array of claim 38, wherein the diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm.

47. The array of claim 46, wherein the memory cells of the array are spaced from each other by between about 220 nm and about 10 nm.

48. The array of claim 38, wherein some memory cells of the array are laterally spaced relative to each other, and wherein other memory cells of the array are stacked on top of each other.

49. The array of claim 48, wherein some of the memory cells of the array that are stacked on top of each other share a bit line.

50. The array of claim 49, wherein some of the memory cells of the array that are laterally spaced relative to each other share a word line.

51. The array of claim 38, wherein the plurality of word lines are substantially perpendicular to the plurality of bit lines.

52. The array of claim 38, wherein the thickness of the nanotube block is between about 10 nm and about 200 nm.

53. The array of claim 38, wherein the thickness of the nanotube block is between about 10 nm and about 50 nm.

54. A high-density memory array, comprising:

a plurality of word lines and a plurality of bit lines;

a plurality of memory cell pairs, each memory cell pair comprising;

a first memory cell comprising a first conductive terminal, a first nanotube element over the first conductive terminal, a second conductive terminal over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and with a first bit line of the plurality of bit lines; and

a second memory cell comprising a third conductive terminal, a second nanotube element over the first conductive terminal, a fourth conductive terminal over the nanotube element, and a second diode in electrical communication with one of the third and fourth conductive terminals and with a second bit line of the plurality of bit lines,

wherein the second memory cell is positioned over the first memory cell, and

wherein the first and second memory cell share a word line of the plurality of word lines;

wherein each memory cell pair of the plurality of memory cells is capable of switching between at least four different resistance states corresponding to four different logic states in response to electrical stimuli at the first and second bit lines and the shared word line.

55. A high-density memory array, comprising:

a plurality of word lines and a plurality of bit lines;

a plurality of memory cell pairs, each memory cell pair comprising;

a first memory cell comprising a first conductive terminal, a first nanotube element over the first conductive terminal, a second conductive terminal over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and with a first word line of the plurality of word lines; and

a second memory cell comprising a third conductive terminal, a second nanotube element over the first conductive terminal, a fourth conductive terminal over the nanotube element, and a second diode in electrical communication with one of the third and fourth conductive terminals and with a second word line of the plurality of word lines,

wherein the second memory cell is positioned over the first memory cell, and

wherein the first and second memory cell share a bit line of the plurality of bit lines;

wherein each memory cell pair of the plurality of memory cells is capable of switching between at least four different resistance states corresponding to four different logic states in response to electrical stimuli at the first and second word lines and the shared bit line.