MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING MAILBOX AREAS AND MAILBOX ACCESS CONTROL METHOD THEREOF
First Claim
1. A semiconductor memory device having N number of ports, the device comprising;
- at least one shared memory area provided in a memory cell array, operationally connected to the N number of ports, and accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one shared memory area, among the N number of ports; and
N number of mailbox areas for message communication provided in one-to-one correspondence with the N number of ports and accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device.
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Accused Products
Abstract
A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.
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Citations
30 Claims
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1. A semiconductor memory device having N number of ports, the device comprising;
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at least one shared memory area provided in a memory cell array, operationally connected to the N number of ports, and accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one shared memory area, among the N number of ports; and N number of mailbox areas for message communication provided in one-to-one correspondence with the N number of ports and accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory device having N number of ports, comprising:
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at least one shared memory area provided in a memory cell array, operationally connected to the N number of ports, and accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one shared memory area, among the N number of ports; and N number of mailbox areas accessible through a plurality of message input/output lines, which are provided per port for message communication between the N number of ports, are separately disposed in parallel to the plurality of data input/output lines, and serve as a message access path, when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of controlling an access to a mailbox in a semiconductor memory device having a shared memory area accessed through at least two ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device, and adapted to perform a message communication between the at least two ports, the method comprising:
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preparing pairs of main and local mailbox blocks as many as the number of ports, each pair of main and local mailbox blocks corresponding to one of the at least two ports, each local mailbox block including a plurality of local mailboxes that each are capable of being connected to a corresponding port through a data access path serving as a shared path for the shared memory area, and each main mailbox block including a plurality of main mailboxes that each are capable of being directly connected to a corresponding port without using the shared path; and performing a control so that when a predetermined port of the at least two ports has an access right to the shared memory area, a message writing operation on all of main mailboxes and local mailboxes corresponding to the predetermined port and a message reading operation on some main mailboxes, having messages to the predetermined port, among the main mailboxes corresponding to the other ports are performed through the predetermined port, and so that when the predetermined port does not have the access right to the shared memory area, a message writing operation on the main mailboxes corresponding to the predetermined port and a message reading operation on some local mailboxes, having messages to the predetermined port, among the local mailboxes corresponding to the other ports are performed through the predetermined port. - View Dependent Claims (26)
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27. A method of controlling an access to a mailbox in a semiconductor memory device having a shared memory area accessed through at least two ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device, and adapted to perform a message communication between the at least two ports, the method comprising:
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preparing pair of main and local mailbox blocks as many as the number of ports, each pair of main and local mailbox blocks corresponding to one of the at least two ports, each local mailbox block including a plurality of local mailboxes that are accessible through a common message input/output line separate from data input/output lines for a data access to the shared memory area, and each main mailbox block including a plurality main mailboxes that are accessible through a corresponding port without using the common message input/output line; and performing a control so that a message writing operation through a predetermined port of the at least two ports is performed on only at least one mailbox corresponding to the predetermined port and the written messages are serially transmitted through the common message input/output line and written to the at least one local mailbox corresponding to the predetermined port, and a message reading operation through the predetermined port is performed on some local mailboxes, having messages to the predetermined port, among the local mailboxes corresponding to the other ports.
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28. A semiconductor memory device, comprising:
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a first local mailbox block having a plurality of local mailboxes; a first main mailbox block having a plurality of first main mailboxes; a first common message input/output line interposed between the first local mailbox block and the first main mailbox block; and a mailbox sub decoder to selectively couple any one of the plurality of first local mailboxes and any one of the plurality of first main mailboxes to the first common message input/output line. - View Dependent Claims (29)
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30. A computer-readable recording medium having embodied thereon a computer program to execute a method of controlling an access to a plurality of mailboxes in a semiconductor memory device having a shared memory area accessed through a plurality of ports and a mailbox area accessed when an address of a predetermined area of the shared memory area is applied to the semiconductor memory device and adapted to perform a message communication between the plurality of ports, wherein the method comprises:
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preparing pairs of main and local mailboxes provided in one-to-one correspondence with the plurality of ports, each local mailbox block including a plurality of local mailboxes that are accessible through a data access path for the shared memory area serving as a shared path, and each main mailbox block including a plurality of main mailboxes that are accessible without using the shared path; and performing a control so that a predetermined port of the plurality of ports has an access right to the shared memory area, a message writing operation on all of main and local mailboxes corresponding to the predetermined port is performed and a message reading operation on some main mailboxes, having messages to the predetermined port, among the main mailboxes corresponding to the other ports is performed, and so that when the predetermined port does not have the access right to the shared memory area, a message writing operation on the main mailboxes corresponding to the predetermined port and a message reading operation on some local mailboxes, having messages to the predetermined ports, among the local mailboxes corresponding to the other ports are performed.
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Specification