SINGLE TRANSDUCER FULL DUPLEX TALKING CIRCUIT
First Claim
Patent Images
1. A single-transducer full duplex circuit, comprising:
- connecting terminals for connecting to an external digital circuit including an input terminal (DIN) which a digital reception input signal is input, an output terminal (DOUT) into which a digital transmission output signal is output, and a learning activation input terminal (ILN);
an analog signal processing circuit including;
an analog differential output amplifier (ADO) which amplifies the output from a D/A converter (DAC);
a bridge circuit consisting of first, second, and third resistors (R1, R2, and R3) and a single transducer (ZT) which are driven by an output of said analog differential output amplifier (ADO); and
an analog differential input amplifier (ADI) which amplifies an equilibrium signal output by said bridge circuit, wherein an analog output signal of said analog differential input amplifier (ADI) is supplied to an A/D converter (ADC);
a digital signal processing circuit including;
a signal generator (SG);
a first high pass filter (HPF1) into which said digital reception input signal is input through said input terminal (DIN);
a first multiplier (MUL1) which multiplies the output of said high pass filter (HPF1) by a reception volume coefficient (RRXV);
a second multiplier (MUL2) which multiplies the input from said signal generator (SG) by a signal volume coefficient register (RSGV);
an adder (ADD) which adds the output of said first multiplier (MUL1) and the output of said second multiplier (MUL2), wherein the output of said adder (ADD) is supplied to said D/A converter (DAC) which converts it into an analog signal;
a first signal delayer and power calculator (DL1) which delays the output signal of said adder (ADD) and calculates a first moving average power value (PW1);
a second signal delayer and power calculator (DL2) which delays the output of said first signal delayer and power calculator (DL1) and calculates a second moving average power value (PW2);
a delayed signal memory (XA[k]) which sequentially stores the output of said second signal delayer and power calculator (DL2);
a transfer function identification filter (FILID) into which the output of said delayed signal memory (XA[k]) is input;
a first filter coefficient memory (HA[k]) which stores a filter coefficient corresponding to said transfer function identification filter (FILID);
a second high pass filter (HPF2) into which an output of said A/D converter (ADC) is input;
a fourth signal delayer (DL4) into which an output of said second high pass filter (HPF2) is input;
a subtracter (SUB) which subtracts an output of said transfer function identification filter (FILID) from an output of said fourth signal delayer (DL4);
a fourth multiplier (MUL4) which multiplies an output of said subtracter (SUB) by a transmission volume coefficient (RTXV);
a third signal delayer and power calculator (DL3) which delays an output of said fourth multiplier (MUL4) and calculates a third moving average power value (PW3);
an equalization filter (FILEQ) into which an output of said third signal delayer and power calculator (DL3) is input; and
a second filter coefficient memory which stores a filter coefficient (HEQ[k]) of said equalization filter (FILEQ),wherein the transmission output terminal (DOUT) is driven by a digital transmission output signal output from said equalization filter (FILEQ) and the first filter coefficient (HA[k]) corresponding to said transfer function identification filter FILID identifies the transfer function from the input end of said D/A converter (ADC) to the output end of said second high pass filter (HPF2) via said analog signal processing circuit.
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Abstract
A full duplex talking audio circuit uses a single transducer ZT which, even when various characteristics including the strength of a transmission signal change from moment to moment, enables the adequate operation of an echo canceling function and sufficiently compensates for the deterioration of the frequency characteristics of the transmission signal due to the acoustic transfer characteristics of the human body.
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Citations
13 Claims
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1. A single-transducer full duplex circuit, comprising:
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connecting terminals for connecting to an external digital circuit including an input terminal (DIN) which a digital reception input signal is input, an output terminal (DOUT) into which a digital transmission output signal is output, and a learning activation input terminal (ILN); an analog signal processing circuit including; an analog differential output amplifier (ADO) which amplifies the output from a D/A converter (DAC); a bridge circuit consisting of first, second, and third resistors (R1, R2, and R3) and a single transducer (ZT) which are driven by an output of said analog differential output amplifier (ADO); and an analog differential input amplifier (ADI) which amplifies an equilibrium signal output by said bridge circuit, wherein an analog output signal of said analog differential input amplifier (ADI) is supplied to an A/D converter (ADC); a digital signal processing circuit including; a signal generator (SG); a first high pass filter (HPF1) into which said digital reception input signal is input through said input terminal (DIN); a first multiplier (MUL1) which multiplies the output of said high pass filter (HPF1) by a reception volume coefficient (RRXV); a second multiplier (MUL2) which multiplies the input from said signal generator (SG) by a signal volume coefficient register (RSGV); an adder (ADD) which adds the output of said first multiplier (MUL1) and the output of said second multiplier (MUL2), wherein the output of said adder (ADD) is supplied to said D/A converter (DAC) which converts it into an analog signal; a first signal delayer and power calculator (DL1) which delays the output signal of said adder (ADD) and calculates a first moving average power value (PW1); a second signal delayer and power calculator (DL2) which delays the output of said first signal delayer and power calculator (DL1) and calculates a second moving average power value (PW2); a delayed signal memory (XA[k]) which sequentially stores the output of said second signal delayer and power calculator (DL2); a transfer function identification filter (FILID) into which the output of said delayed signal memory (XA[k]) is input; a first filter coefficient memory (HA[k]) which stores a filter coefficient corresponding to said transfer function identification filter (FILID); a second high pass filter (HPF2) into which an output of said A/D converter (ADC) is input; a fourth signal delayer (DL4) into which an output of said second high pass filter (HPF2) is input; a subtracter (SUB) which subtracts an output of said transfer function identification filter (FILID) from an output of said fourth signal delayer (DL4); a fourth multiplier (MUL4) which multiplies an output of said subtracter (SUB) by a transmission volume coefficient (RTXV); a third signal delayer and power calculator (DL3) which delays an output of said fourth multiplier (MUL4) and calculates a third moving average power value (PW3); an equalization filter (FILEQ) into which an output of said third signal delayer and power calculator (DL3) is input; and a second filter coefficient memory which stores a filter coefficient (HEQ[k]) of said equalization filter (FILEQ), wherein the transmission output terminal (DOUT) is driven by a digital transmission output signal output from said equalization filter (FILEQ) and the first filter coefficient (HA[k]) corresponding to said transfer function identification filter FILID identifies the transfer function from the input end of said D/A converter (ADC) to the output end of said second high pass filter (HPF2) via said analog signal processing circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An audio circuit, comprising:
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an analog circuit including a differential output amplifier, an differential input amplifier, and a bridge circuit coupled between the differential output amplifier and the differential input amplifier; and a digital signal processing circuit configured to generate one or more first set of signal filter coefficients from a first signal input into the analog circuit and generate one or more second set of filter coefficients from a second signal output from the analog circuit, the digital signal processing circuit generating an transfer function from the first and second set of filter coefficients and generating an output signal from the transfer function that is applied to the second signal output from the analog circuit. - View Dependent Claims (11, 12, 13)
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Specification