MEMORY CONTROLLER AND METHOD OF CONTROLLING A MEMORY

• US 20080172534A1
• Filed: 01/16/2007
• Published: 07/17/2008
• Est. Priority Date: 01/16/2007
• Status: Active Grant

• Current Assignee: Maxlinear Incorporated
• Original Assignee: Lantiq Deutschland GMBH (Intel Corporation)
• Inventors: Kumar, Ravi Ranjan, Balakrishnan, Prashant, Nagabhushana, Rashmi H.
• Granted Patent: US 7,788,414 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.

Claims

1. A memory controller, comprising:

a control circuit configured to provide a control signal;

an output interface unit; and

a command storage unit coupled to the control circuit and the output interface and configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.

2. The memory controller of claim 1, wherein the command storage unit is programmable.

3. The memory controller of claim 2, comprising:

a command programming interface unit coupled to the command storage unit, wherein at least one command of the plurality of commands is stored into the command storage unit via the command programming interface unit.

4. The memory controller of claim 1, wherein the plurality of commands comprises at least one of an initialization command sequence, a write command sequence, a read command sequence, and an autorefresh command sequence.

5. The memory controller of claim 1, wherein the output interface unit is coupled to a memory interface and is configured to provide the selected command to the memory interface.

6. The memory controller of claim 1, wherein the selected command comprises at least one memory command signal for a memory interface.

7. The memory controller of claim 6, wherein the at least one memory command signal comprises at least one of a value for a chip select (CS) signal, a row access strobe (RAS) signal, a column access strobe (CAS) signal, a write enable (WE) signal, and a clock enable (CKE) signal associated with the command.

8. The memory controller of claim 1, wherein the selected command is selected from the plurality of commands based on the control signal.

9. The memory controller of claim 1, comprising:

at least one input configured to receive a write request or a read request; and

wherein the control circuit is coupled to the input and is configured to provide the control signal to the command storage unit responsive to the write request or the read request.

10. The memory controller of claim 1, wherein the command storage unit is configured to store control information associated with the command and provide the control information to the control circuit.

11. The memory controller of claim 10, wherein the control circuit is configured to generate a new control signal based on the control information.

12. A memory controller, comprising:

a first interface;

a second interface;

a programmable register unit coupled to the first interface and the second interface and configured to receive at least one command via the first interface and store the at least one command; and

a control circuit coupled to the programmable register unit and configured to control outputting of a command from the programmable register unit to the second interface.

13. The memory controller of claim 12, wherein the programmable register unit is configured to store at least one command sequence received via the first interface.

14. The memory controller of claim 12, wherein the command output from the programmable register unit comprises at least one memory command signal for a memory.

15. The memory controller of claim 12, comprising:

a control input coupled to the control circuit; and

wherein the control circuit has a plurality of operation modes, wherein a selected operation mode of the plurality of operation modes is selected by a signal received at the control input.

16. The memory controller of claim 12, comprising:

a third interface coupled to the control circuit; and

wherein the control circuit is configured to receive at least one of a write request, a read request, an initialization request, and an autorefresh request for a memory at the third interface and control outputting of the command from the programmable register unit based on the request.

17. The memory controller of claim 16, wherein the control circuit is configured to receive the request and a successive request at the third interface and control outputting of the command from the programmable register unit based on both the request and the successive request.

18. A memory controller, comprising:

a first interface;

a second interface;

a programmable first register unit coupled to the first interface and the second interface and configured to store at least one command received via the first interface; and

a control circuit coupled to the first register unit and configured to control outputting of a command of the at least one command from the first register unit to the second interface; and

wherein the first register unit is configured to store control information associated with the command output from the first register unit.

19. The memory controller of claim 18, wherein the first register unit is configured to receive the control information via the first interface and store the control information.

20. The memory controller of claim 18, wherein the first register unit is configured to provide the control information to the control circuit when the command is output to the second interface.

21. The memory controller of claim 20, wherein the control information comprises delay count information.

22. The memory controller of claim 21, wherein the control circuit is configured to control a delay between commands output from the first register unit based on the delay count information.

23. The memory controller of claim 20, comprising:

a second register unit coupled to the control circuit and configured to store second control information; and

wherein the control circuit is configured to retrieve the second control information from the second register unit in response to and based on the control information.

24. The memory controller of claim 23, wherein the second control information comprises at least one of an autorefresh count, an operation mode information, and a delay count information.

25. The memory controller of claim 20, wherein the control information comprises repeat count information.

26. The memory controller of claim 25, wherein the control circuit is configured to control repeated outputting of the command based on the repeat count information.

27. A memory unit, comprising:

a memory;

a memory interface unit coupled to the memory; and

a memory controller coupled to the memory interface unit and comprising;

means for storing a plurality of commands; and

means for controlling outputting of a command from the means for storing a plurality of commands to the memory interface unit.

28. The memory unit of claim 27, comprising:

a buffer manager coupled to the memory controller to provide a write request or read request to the memory controller, wherein the means for controlling outputting of a command controls outputting of the command in response to the write request or the read request.

29. The memory unit of claim 27, comprising:

a further memory interface unit; and

a further memory controller coupled to the further memory interface unit and comprising the means for storing a plurality of commands.

30. The memory unit of claim 29, wherein the further memory controller comprises a further means for controlling outputting of a command from the means for storing a plurality of commands to the further memory interface unit.

31. A method of controlling a memory, comprising:

providing a memory controller coupled to the memory and comprising a programmable command storage unit having stored therein a plurality of commands;

retrieving a command of the plurality of commands from the command storage unit; and

outputting the command from the memory controller to the memory.

32. The method of claim 31, comprising:

storing at least one command of the plurality of commands in the command storage unit.

33. The method of claim 32, comprising:

storing control information associated with the at least one command in the command storage unit.

34. The method of claim 33, comprising:

selecting an operation mode for the memory, wherein the control information is stored in the command storage unit based on the operation mode.

35. The method of claim 31, wherein the command comprises at least one of a value for a chip select (CS) signal, a row access strobe (RAS) signal, a column access strobe (CAS) signal, a write enable (WE) signal, and a clock enable (CKE) signal associated with the command.

36. A method of controlling a memory, comprising:

providing a memory controller having a plurality of operation modes and comprising a programmable register unit;

selecting an operation mode for the memory controller; and

storing a plurality of commands in the programmable register unit based on the selected operation mode.

37. The method of claim 36, comprising:

providing a memory; and

outputting a command of the plurality of commands from the register unit to the memory.