SEMICONDUCTOR DEVICE

• US 20080173899A1
• Filed: 01/07/2008
• Published: 07/24/2008
• Est. Priority Date: 01/22/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: TAKAKUWA, Koichiro, Tanaka, Kazuo
• Application Number:
  US11/970,512
• Publication Number:
  US 20080173899A1
• Time in Patent Office: Days
• US Class Current: 257/203
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

There is provided a technology which allows sufficient protection of internal circuits from electrostatic discharge even when internal-circuit power source pads and internal-circuit GND pads are formed on an internal circuit region. Internal-circuit power source pads and internal-circuit GND pads are placed in the core region of a semiconductor chip. Between the internal-circuit power source pads and the internal-circuit GND pads, the internal circuits are formed. Between the internal-circuit power source pads and the internal-circuit GND pads, electrostatic protection circuits for protecting the internal circuits from a surge current are further formed. Each of the electrostatic protection circuits is composed of a discharge circuit for causing the surge current to flow therein and a control circuit for controlling the discharge circuit. The present invention is characterized in that the discharge circuits are placed in the core region and the control circuits are placed in an I/O region.

Claims

1. A semiconductor device comprising a semiconductor chip including:

(a) an I/O region in which an input/output circuit serving as an interface with an external circuit is formed; and

(b) an internal circuit region which is other than the I/O region and in which an internal circuit is formed, wherein an internal-circuit power source pad for supplying a source power to the internal circuit is formed on the internal circuit region,

wherein an electrostatic protection circuit is coupled to the internal-circuit power source pad, and

wherein a circuit composing part of the electrostatic protection circuit is formed in the internal circuit region.

2. A semiconductor device according to claim 1,

wherein the electrostatic protection circuit has a discharge circuit for discharging a surge current and a control circuit for controlling the discharge circuit, and

wherein the discharge circuit is formed in the internal circuit region.

3. A semiconductor device according to claim 2, wherein the control circuit is formed in the I/O region.

4. A semiconductor device according to claim 1,

wherein the semiconductor chip has a rectangular shape,

wherein the I/O region is formed along an outer peripheral portion of the semiconductor chip, and

wherein the internal circuit region is formed in an inner region than the I/O region.

5. A semiconductor device according to claim 4,

wherein the electrostatic protection circuit has a discharge circuit for discharging a surge current and a control circuit for controlling the discharge circuit, and

wherein the discharge circuit is formed in the internal circuit region.

6. A semiconductor device according to claim 5, wherein the control circuit is formed in the I/O region.

7. A semiconductor device according to claim 6, wherein the control circuit is formed at a corner portion of the semiconductor chip.

8. A semiconductor device according to claim 5, wherein the discharge circuit is formed in an inner peripheral portion of the internal circuit region.

9. A semiconductor device according to claim 8, wherein the discharge circuit is formed outside the internal-circuit power source pad.

10. A semiconductor device according to claim 2, wherein a plurality of the discharge circuits are coupled to the single control circuit.

11. A semiconductor device according to claim 2,

wherein the internal circuit is formed using a standard cell composed of a p-channel MISFET and an n-channel MISFET as a unit element, and

wherein the discharge circuit is formed using the standard cell.

12. A semiconductor device according to claim 11, wherein the discharge circuit is composed of an inverter and an n-channel MISFET.

13. A semiconductor device according to claim 11, wherein the discharge circuit is composed of an inverter and a plurality of n-channel MISFETs.

14. A semiconductor device according to claim 3, wherein the control circuit is composed of a resistor element and a capacitor element.

15. A semiconductor device according to claim 3,

wherein the control circuit is composed of a first MISFET and a second MISFET, and

wherein the first MISFET functions as a resistor element and the second MISFET functions as a capacitor element.