ENHANCED MOBILITY CMOS TRANSISTORS WITH A V-SHAPED CHANNEL WITH SELF-ALIGNMENT TO SHALLOW TRENCH ISOLATION
First Claim
1. A semiconductor structure, comprising:
- a semiconductor substrate with a substrate orientation;
a V-shaped groove with a ridge and a first crystallographic facet and a second crystallographic facet of a semiconductor material, wherein said V-shaped groove is bounded by shallow trench isolation and said first crystallographic facet and said second crystallographic facet are joined by said ridge;
a channel located beneath said V-shaped groove, said channel adjoining a portion of said ridge, a portion of said first crystallographic facet, and a portion of said second crystallographic facet;
a source adjoined to said channel and located on said ridge;
a drain adjoined to said channel and not adjoined to said source and located on said ridge;
a gate dielectric adjoined to and located above said channel; and
a gate conductor adjoined to said gate dielectric and not adjoined to said channel, said source and said drain.
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Accused Products
Abstract
The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
184 Citations
20 Claims
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1. A semiconductor structure, comprising:
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a semiconductor substrate with a substrate orientation; a V-shaped groove with a ridge and a first crystallographic facet and a second crystallographic facet of a semiconductor material, wherein said V-shaped groove is bounded by shallow trench isolation and said first crystallographic facet and said second crystallographic facet are joined by said ridge; a channel located beneath said V-shaped groove, said channel adjoining a portion of said ridge, a portion of said first crystallographic facet, and a portion of said second crystallographic facet; a source adjoined to said channel and located on said ridge; a drain adjoined to said channel and not adjoined to said source and located on said ridge; a gate dielectric adjoined to and located above said channel; and a gate conductor adjoined to said gate dielectric and not adjoined to said channel, said source and said drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor structure, comprising:
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a semiconductor substrate with a substrate orientation; a V-shaped groove with a ridge and a first crystallographic facet and a second crystallographic facet of a semiconductor material, wherein said first crystallographic facet and said second crystallographic facet are joined by said ridge; a frame of constant width of semiconductor surface, said frame surrounding said V-shaped groove and bounded by and self-aligned to shallow trench isolation; a channel located beneath said V-shaped groove, said channel adjoining a portion of said ridge, a portion of said first crystallographic facet, a portion of said second crystallographic facet, and at least one portion of said frame; a source adjoined to said channel and located on said ridge; a drain adjoined to said channel and not adjoined to said source and located on said ridge; a gate dielectric adjoined to and located above said channel; and a gate conductor adjoined to said gate dielectric and not adjoined to said channel, said source and said drain. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method of fabricating a semiconductor structure, comprising:
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providing a semiconductor substrate with a substrate orientation; subjecting a portion of said semiconductor to at least one an etchant with an anisotropic etch rate along different crystallographic planes; forming at least two new facets which are joined with a V-shaped cross-sectional profile with surface orientations that are at an angle substantially greater than zero degree to said substrate orientation and is substantially not orthogonal to said substrate orientation; and forming a gate dielectric on said at least one facet. - View Dependent Claims (17, 18, 19, 20)
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Specification