ELECTRONIC DEVICE INCLUDING TRENCHES AND DISCONTINUOUS STORAGE ELEMENTS AND PROCESSES OF FORMING AND USING THE SAME

• US 20080173921A1
• Filed: 01/24/2007
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong Min, Li, Chi-Nan
• Granted Patent: US 7,838,922 B2
• Time in Patent Office: Days
• US Class Current: 257/311
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate outside of the trench, and a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench. The electronic device can also include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench. Processes of forming and using the electronic device are also described.

Claims

1. An electronic device comprising:

a substrate including a trench having a bottom and a first wall;

a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench;

a second gate electrode overlying the substrate outside of the trench;

a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench; and

discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench.

2. The electronic device of claim 1, further comprising a first source/drain region and a second source/drain region, wherein:

the first source/drain region lies within the substrate below the bottom of the trench and adjacent to the third gate electrode; and

the second source/drain region lies within the substrate outside of the trench and adjacent to the second gate electrode.

3. The electronic device of claim 2, wherein the first gate electrode, the second gate electrode, the third gate electrode, the first set of discontinuous storage elements, the first source/drain region, and the second source/drain region are parts of a first memory cell.

4. The electronic device of claim 3, further comprising:

a fourth gate electrode within the trench and adjacent to a second wall of the trench and overlying the bottom of the trench;

a fifth gate electrode overlying the substrate outside of the trench;

a sixth gate electrode within the trench and adjacent to the fourth gate electrode and overlying the bottom of the trench; and

a third source/drain region lying within the substrate outside of the trench and adjacent to the fifth gate electrode,

wherein;

the discontinuous storage elements includes a second set of discontinuous storage elements, wherein the second set of the discontinuous storage elements lies adjacent to the second wall of the trench; and

the fourth gate electrode, the fifth gate electrode, the sixth gate electrode, the second set of discontinuous storage elements, the second source/drain region, and the third source/drain region are parts of a second memory cell.

5. The electronic device of claim 4, wherein each of the first memory cell and the second memory cell is operable to store 2 bits of data.

6. The electronic device of claim 2, wherein the first set of discontinuous storage elements lies between the first gate electrode and the first wall.

7. The electronic device of claim 1, wherein each of the first gate electrode, the second gate electrode, and third gate electrode has an arc-shaped edge.

8. The electronic device of claim 7, wherein the third gate electrode comprises a base, and the first set of the discontinuous storage elements also underlies the base of the third gate electrode.

9. The electronic device of claim 1, wherein:

the discontinuous storage elements includes a second set of discontinuous storage elements;

the first set of discontinuous storage elements lies between the second gate electrode and the substrate; and

the second set of discontinuous storage elements lies between the third gate electrode and the bottom of the trench.

10. The electronic device of claim 9, wherein the first gate electrode, the second gate electrode, the third gate electrode, the first set of discontinuous storage elements, and the second set of discontinuous storage elements are parts of a memory cell operable to store 4 bits of data.

20. The process of claim 8, further comprising erasing the memory cell comprising:

biasing the substrate and the first gate electrode at a fourth voltage difference, such that the fourth voltage difference has an opposite polarity compared to first voltage difference, and the fourth voltage difference has a magnitude that is at least approximately 4 times a magnitude of the first voltage difference; and

electrically floating the first bit line and the second bit line.

11. A process of forming an electronic device comprising:

providing a substrate having a primary surface;

forming a patterned sacrificial layer over the primary surface of the substrate;

forming a trench extending from the primary surface of the substrate, wherein the trench has a first wall and a bottom;

forming discontinuous storage elements over the primary surface and within the trench;

forming a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, wherein a portion of the first gate electrode lies at an elevation higher than the primary surface and adjacent to the patterned sacrificial layer;

removing the patterned sacrificial layer after forming the first gate electrode;

forming a second gate electrode outside the trench and adjacent to the first gate electrode, wherein forming the second gate electrode is performed after removing the patterned sacrificial layer; and

removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench.

12. The process of claim 11, further comprising forming a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench.

13. The process of claim 12, wherein forming the first gate electrode comprises:

forming a first gate material over the substrate outside the trench and adjacent to the first wall and the bottom of the trench, wherein forming the first gate material only partly fills the trench; and

anisotropically etching the first gate material to form the first gate electrode.

14. The process of claim 13, wherein forming the second gate electrode and forming the third gate electrode comprises:

forming a second gate material over the substrate outside the trench and adjacent to the first wall and the bottom of the trench, wherein forming the second gate material is performed after forming the first gate electrode; and

anisotropically etching the second gate material to form the second gate electrode and the third gate electrode.

15. The process of claim 14, further comprising:

forming a fourth gate electrode within the trench and adjacent to a second wall of the trench and overlying the bottom of the trench, wherein forming the first gate electrode and forming the fourth gate electrode are performed substantially simultaneously;

forming a fifth gate electrode outside the trench and adjacent to the fourth gate electrode;

forming a sixth gate electrode within the trench and adjacent to the fourth gate electrode and overlying the bottom of the trench, wherein forming the second gate electrode, forming the third gate electrode, forming the fifth gate electrode, and forming the sixth gate electrode are performed substantially simultaneously; and

forming a first source/drain region, a second source/drain region, and a third source drain region, wherein;

the first source/drain region lies outside the trench and adjacent to the second gate electrode;

the second source/drain region lies within the substrate beneath the bottom of the trench and adjacent to the third gate electrode and the sixth gate electrode; and

the third source/drain region lies outside the trench and adjacent to the fifth gate electrode.

16. The process of claim 11, wherein:

forming the discontinuous storage elements is performed before forming the first gate electrode; and

removing the portion of the discontinuous storage elements is performed after forming the first gate electrode and before forming the second gate electrode.

17. The process of claim 11, wherein:

forming the discontinuous storage elements is performed after forming the first gate electrode and before forming the second gate electrode; and

removing the portion of the discontinuous storage elements is performed after forming the second gate electrode, wherein removing the portion also forms a second set of discontinuous storage elements, wherein the first set of discontinuous storage elements lies between the second gate electrode and the substrate.

18. A process of using an electronic device comprising:

providing a memory cell including;

a substrate including a trench having a bottom and a first wall;

a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench;

a second gate electrode overlying the substrate outside of the trench;

a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench;

a first source/drain region adjacent to the third gate electrode and coupled to a first bit line;

a second source/drain region adjacent to the second gate electrode and coupled to a second bit line; and

discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench; and

programming a first bit of the memory cell comprising;

biasing the first bit line and the second bit line at a first voltage difference;

biasing the third gate electrode, such that a second voltage difference between the third gate electrode and the first bit line is no greater than approximately half of the first voltage difference;

biasing the first gate electrode, such that a third voltage difference between the first gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference; and

biasing the second gate electrode, such that a fourth voltage difference between the second gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference.

19. The process of claim 18, further comprising programming a second bit of the memory cell comprising:

biasing the first bit line and the second bit line at a fifth voltage difference;

biasing the second gate electrode, such that a sixth voltage difference between the second gate electrode and the second bit line is no greater than approximately half of the fifth voltage difference;

biasing the first gate electrode, such that a seventh voltage difference between the first gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the fifth voltage difference; and

biasing the third gate electrode, such that an eighth voltage difference between the third gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the fifth voltage difference.