ELECTRONIC DEVICE INCLUDING FINS AND DISCONTINUOUS STORAGE ELEMENTS AND PROCESSES OF FORMING AND USING THE SAME

• US 20080173922A1
• Filed: 01/24/2007
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: LI, Chi-Nan, HONG, Cheong Min
• Granted Patent: US 7,572,699 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.

Claims

1. An electronic device comprising:

a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide;

a first gate electrode within the first trench and adjacent to the fin;

a second gate electrode within the second trench and adjacent to the fin; and

discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin.

2. The electronic device of claim 1, wherein:

the substrate has a primary surface;

the first gate electrode has a first upper surface that lies at a first elevation not significantly higher than the primary surface of the substrate; and

the second gate electrode has a second upper surface that lies at a second elevation not significantly higher than the primary surface of the substrate.

3. The electronic device of claim 1, wherein each of the first gate electrode and the second gate electrode includes a control/select gate electrode.

4. The electronic device of claim 1, wherein substantially all discontinuous storage elements lie within the trenches, including the first trench and the second trench, within the substrate.

5. The electronic device of claim 1, wherein:

the first set of the discontinuous storage elements also underlies a first base of the first gate electrode; and

the second set of the discontinuous storage elements also underlies a second base of the second gate electrode.

6. The electronic device of claim 1, wherein the fin has a width in a range of approximately 10 nm to approximately 50 nm.

7. The electronic device of claim 1, further comprising a third gate electrode overlying the fin.

8. The electronic device of claim 7, further comprising:

a first source/drain region lying below the first trench;

a second source/drain region lying below the second trench;

a third source/drain region lying within the fin and adjacent to a first side of the third gate electrode; and

a fourth source/drain region lying within the fin and adjacent to a second side of the third gate electrode opposite the first side.

9. The electronic device of claim 8, wherein:

the first gate electrode, the second gate electrode, the first source/drain region, and the second source/drain region are parts of a first memory cell; and

the third gate electrode, the third source/drain region, and the fourth source/drain region are parts of a second memory cell.

10. The electronic device of claim 9, further comprising:

a first bit line coupled to the first source/drain region;

a second bit line coupled to the second source/drain region;

a third bit line coupled to the third source/drain region; and

a fourth bit line coupled to the fourth source/drain region, wherein;

the electronic device includes a memory array of memory cells, including the first memory cell and the second memory cell;

the first bit line and the second bit line are oriented substantially perpendicular to the third bit line and the fourth bit line; and

the first gate electrode and the second gate electrode are oriented substantially perpendicular to the third gate electrode.

11. A process of forming an electronic device comprising:

forming a first trench and a second trench within a substrate, wherein a portion of the substrate lies between the first trench and the second trench, and has a width of no more than approximately 90 nm;

forming discontinuous storage elements within the first trench and the second trench;

forming a first gate electrode within the first trench and a second gate electrode within the second trench; and

removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the portion of the substrate, and the second set of the discontinuous storage elements lies between the second gate electrode and the portion of the substrate.

12. The process of claim 11, wherein forming the first gate electrode and forming the second gate electrode comprises:

depositing a gate electrode material over the portion of the substrate and along walls and bottoms of the first trench and the second trench; and

anisotropically etching the gate electrode material to remove a portion of the gate electrode material from over the portion of the substrate.

13. The process of claim 11, wherein:

forming the discontinuous storage elements is part of forming a charge storage stack; and

forming the first gate electrode and forming the second gate electrode comprises exposing a portion of the charge storage stack.

14. The process of claim 13, wherein removing the portion of the discontinuous charge storage elements comprises etching the portion of the charge storage stack.

15. The process of claim 13, wherein removing the portion of the discontinuous charge storage elements comprises converting the portion of the discontinuous charge storage elements to an electrically insulating material.

16. The process of claim 11, further comprising doping a first portion of the substrate along a first bottom of the first trench and doping a second portion of the substrate along a second bottom of the second trench.

17. The process of claim 16, further comprising forming a third gate electrode over the fin, wherein the third gate electrode is oriented substantially perpendicular the first gate electrode and the second gate electrode.

18. A process of using an electronic device comprising:

providing a memory cell including;

a substrate, wherein a first trench and a second trench extend therein and are spaced apart from each other by a portion of the substrate;

a first gate electrode within the first trench;

a first source/drain region lying along a first bottom of the first trench, wherein the first source/drain region is coupled to a first bit line;

a second gate electrode within the second trench;

a second source/drain region lying along a second bottom of the second trench, wherein the first source/drain region is coupled to a second bit line; and

discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and a first bottom of the first trench, and the second set of the discontinuous storage elements lies between the second gate electrode and a second bottom of the second trench; and

programming a first bit of the memory cell comprising;

biasing the first bit line and the second bit line at a first voltage difference;

biasing the first gate electrode, such that a second voltage difference between the first gate electrode and the first bit line is no greater than approximately half of the first voltage difference; and

biasing the second gate electrode, such that a third voltage difference between the second gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference, wherein a substantial fraction of current flows underneath the portion of the substrate during programming the first bit.

19. The process of claim 18, further comprising programming a second bit of the memory cell comprising:

biasing the first bit line and the second bit line at a fourth voltage difference;

biasing the first gate electrode, such that a fifth voltage difference between the first gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference; and

biasing the second gate electrode, such that a sixth voltage difference between the second gate electrode and the second bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference.

20. The process of claim 18, further comprising erasing the memory cell comprising:

biasing the substrate and the second gate electrode at a fourth voltage difference, such that the fourth voltage difference has an opposite polarity compared to first voltage difference, and the fourth voltage difference has a magnitude that is at least approximately 4 times a magnitude of the first voltage difference; and

electrically floating the first bit line and the second bit line.