ELECTRONIC DEVICE INCLUDING TRENCHES AND DISCONTINUOUS STORAGE ELEMENTS AND PROCESSES OF FORMING AND USING THE SAME
First Claim
1. An electronic device comprising:
- a substrate including a first trench having a first bottom and a first wall;
a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench;
a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench; and
discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench.
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Accused Products
Abstract
An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.
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Citations
20 Claims
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1. An electronic device comprising:
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a substrate including a first trench having a first bottom and a first wall; a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench; a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench; and discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A process of forming an electronic device comprising:
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forming a first trench within a substrate, wherein the first trench extends from a primary surface of the substrate and has a first wall and a first bottom; forming discontinuous storage elements over the primary surface and within the first trench; forming a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench; forming a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench; and removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A process of using an electronic device comprising:
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providing a memory cell including; a substrate having a primary surface and including a first trench having a first bottom and a first wall; a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench; a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench; discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the first bottom of the first trench, and lies between the first gate electrode and the first wall; programming a first bit of the memory cell comprising; biasing the first bit line and the second bit line at a first voltage difference; biasing the second gate electrode, such that a second voltage difference between the second gate electrode and the first bit line is no greater than approximately half of the first voltage difference; and biasing the first gate electrode, such that a third voltage difference between the first gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference. - View Dependent Claims (19, 20)
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Specification