Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method

• US 20080173931A1
• Filed: 01/19/2007
• Published: 07/24/2008
• Est. Priority Date: 01/19/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Ho, ChiaHua
• Granted Patent: US 7,667,220 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

Claims

1. A memory structure having multiple memory layers, comprising:

a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode, the first electrode having a dimension that is substantially similar to a dimension of the tungsten oxide region; and

a second memory layer structure, coupled to the first memory layer structure, having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure, the first electrode in the second memory layer structure having a dimension that is substantially similar to a dimension of the tungsten oxide region in the second memory layer structure.

2. The memory structure of claim 1, wherein the tungsten oxide region provides a multilevel function in the operation in the first memory layer.

3. The memory structure of claim 1, wherein the first electrode comprises a plug structure filled with tungsten.

4. The memory structure of claim 3, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure.

5. The memory structure of claim 1, further comprising an n-p diode electrically coupled to the first electrode in the first memory layer structure.

6. The memory structure of claim 5, further comprising a first bit line electrically coupled to the p-n diode.

7. The memory structure of claim 1, further comprising a p-n diode electrically coupled to the first electrode in the second memory layer structure.

8. The memory structure of claim 7, further comprising a second bit line electrically coupled between the tungsten oxide region in the first memory layer structure and the p-n diode.

9. The memory structure of claim 8, further comprising a third bit line electrically coupled to the tungsten oxide region in the second memory layer structure.

10. A memory structure having multiple memory layers, comprising:

a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending into the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode; and

a second memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending into the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure.

11. The memory structure of claim 10, wherein the tungsten oxide region provides a multilevel function in the operation in the first memory layer.

12. The memory structure of claim 10, wherein the first electrode comprises a plug structure filled with tungsten.

13. The memory structure of claim 12, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure.

14. The memory structure of claim 10, further comprising an n-p diode electrically coupled to the first electrode in the first memory layer structure.

15. The memory structure of claim 14, further comprising a first bit line electrically coupled to the p-n diode.

16. The memory structure of claim 10, further comprising a p-n diode electrically coupled to the first electrode in the second memory layer structure.

17. The memory structure of claim 16, further comprising a second bit line electrically coupled between the tungsten oxide region in the first memory layer structure and the p-n diode.

18. The memory structure of claim 17, further comprising a third bit line electrically coupled to the tungsten oxide region in the second memory layer structure.

19. A memory structure having multiple memory layers, comprising:

a first memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode and electrically connecting between the first electrode and a second electrode, the first electrode including a plug structure having a first plug portion having a dimension and a second plug portion having a dimension, the dimension of the first plug portion having a smaller value than the dimension of the second plug portion, the tungsten oxide region having a dimension that is substantially similar to the dimension of the first electrode; and

a second memory layer structure having a first electrode with a principle surface and a tungsten oxide region, the tungsten oxide region extending from the principle surface of the first electrode in the second memory layer structure and electrically connecting between the first electrode in the second memory layer structure and a second electrode in the second memory layer structure, the first electrode in the second memory layer structure including a plug structure having a first plug portion having a dimension and a second plug portion having a dimension, the dimension of the first plug portion in the plug structure of the second memory layer structure having a smaller value than the dimension of the second plug portion in the plug structure of the second memory layer structure, the first electrode in the second memory layer structure having a first dimension that is substantially similar to a first dimension of the tungsten oxide region in the second memory layer structure.

20. The memory structure of claim 19, wherein the first plug portion is self-aligned with the second plug portion.

21. The memory structure of claim 20, wherein the first plug portion is not self-aligned with the second plug portion.

22. A method for manufacturing a memory device, comprising:

forming a plug structure with a plug material surrounded by a barrier material and disposed between dielectric members;

etching a top portion of the plug material and the barrier material with a dry etch using a first chemistry followed by a wet recess etch with a second chemistry; and

forming dielectric spacers over a principle surface of the etched plug material;

forming a tungsten oxide region entering the principle surface of the etched plug material by a dry oxygen plasma strip; and

forming a bit line into the dielectric spacers and over the tungsten oxide region.

23. The method of claim 22, wherein the dry etch with the first chemistry comprises a SF6 dry etch.

24. The method of claim 22, wherein the recess etching with the second chemistry comprises a barrier isotropic etch using chlorine, trichloroborane or argon.

25. The method of claim 22, wherein the dry oxygen plasma strip comprises mixed chemistries of O₂/N₂ or O₂/N₂/H₂.

26. The method of claim 22, wherein the dry oxygen plasma strip comprises pure oxygen gas with a plasma including a direct plasma, a magnetic field enhanced reactive ion plasma, or a down-stream plasma.

27. The method of claim 22, wherein the bit line comprises a bit line overlying a barrier layer.