GUARD RING STRUCTURE FOR IMPROVING CROSSTALK OF BACKSIDE ILLUMINATED IMAGE SENSOR

• US 20080173963A1
• Filed: 01/24/2007
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wuu, Shou-Gwo, Hsu, Tzu-Hsuan, Yaung, Dun-Nian
• Granted Patent: US 7,485,940 B2
• Time in Patent Office: Days
• US Class Current: 257/431
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00

Abstract

The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.

Claims

1. A backside illuminated semiconductor device, comprising:

a substrate having a front surface and a back surface;

a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements designed and configured to receive light directed towards the back surface; and

a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent sensor elements of the plurality of sensor elements, and vertically between the back surface and the front surface.

2. The device of claim 1, the sensor isolation feature is designed to reduce at least one of optical and electrical interferences between the two adjacent elements.

3. The device of claim 1, wherein the sensor isolation feature comprises a doped region.

4. The device of claim 3, wherein the doped region comprises a doping concentration ranging between about 10¹⁴ atoms/cm³ and 10²¹ atoms/cm³.

5. The device of claim 3, wherein the sensor isolation feature is designed and applicable for a biasing voltage ranging from about −

1 V to 10 V during operation.

6. The device of claim 3, wherein the sensor isolation feature is designed and configurable for being electrically floating during operation.

7. The device of claim 1, wherein the sensor isolation feature comprises a plug.

8. The device of claim 7, wherein the plug is filled with a material selected from the group consisting of air, a dielectric material, an opaque material, a metal material, and combinations thereof.

9. The device of claim 8, wherein the metal material is selected from the group consisting of aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, metal silicide, and combinations thereof.

10. The device of claim 8, wherein the dielectric material is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, low k material, and combinations thereof.

11. The device of claim 1, wherein the sensor isolation feature comprises a width ranging between about 0.1 micron and about 10 micron.

12. The device of claim 1, wherein the sensor isolation feature comprises a depth ranging between about 10% and 90% of the thickness of the substrate.

13. The device of claim 1, wherein the substrate comprises a thickness ranging between about 0.5 micron and about 500 micron.

14. The device of claim 1, wherein the substrate comprises a portion selected from the group consisting of an epi layer, a semiconductor on insulator (SOI) structure, and combinations thereof.

15. The device of claim 1, wherein each of the plurality of sensor elements is selected from the group consisting of complementary metal-oxide-semiconductor (CMOS) image sensor, charge-coupled device sensor, active pixel sensor, passive pixel sensor, and combinations thereof.

16. A semiconductor device, comprising:

a semiconductor substrate having a front surface and a back surface;

a sensor element disposed in the front surface;

a conductive interconnect feature disposed on the front surface, overlying the sensor element; and

a sensor isolation feature formed in the semiconductor substrate, disposed horizontally around the sensor element and vertically between the back surface and the conductive interconnect feature.

17. The device of claim 16, wherein the sensor isolation feature comprises a material selected from the group consisting of air, a dielectric material, an opaque material, a metal material, a doped material, and combinations thereof.

18. The device of claim 16, wherein the sensor isolation feature is configured to substantially include the sensor element in top view perpendicular to the semiconductor device.

19. The device of claim 16, further comprising a microlens disposed on the back surface, and designed to receive radiation towards the back surface and direct the radiation to the sensor element.

20. A method to fabricate a semiconductor device, comprising:

providing a semiconductor substrate having a front surface and a back surface;

forming a sensor element in the front surface;

forming conductive interconnect on the front surface, overlying the sensor element; and

forming a sensor isolation feature in the semiconductor substrate, disposed horizontally around

the sensor element and vertically between the back surface and the conductive interconnect.

21. The method of claim 20, wherein the forming of the sensor isolation feature comprises forming a plug filled with a material selected from the group consisting of air, a dielectric material, an opaque material, a metal material, and combinations thereof.

22. The method of claim 20, wherein the forming of the sensor isolation feature comprises forming a doped region.