Configuration of high-voltage semiconductor power device to achieve three dimensionalcharge coupling

• US 20080173969A1
• Filed: 01/22/2007
• Published: 07/24/2008
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Feng, Tao, Hebert, Francois
• Granted Patent: US 7,670,908 B2
• Time in Patent Office: Days
• US Class Current: 257/488
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Claims

1. A semiconductor device comprising:

a top region and a bottom region with an intermediate region disposed between said top region and said bottom region;

a controllable current path traversing through said intermediate region;

an insulating trench extended from said top region through said intermediate region toward said bottom region wherein said insulating trench comprising randomly and substantially uniformly distributed nano-nodules as charge-islands for electrically coupling with said intermediate region for continuously and uniformly distributing a voltage drop through said current path.

2. The semiconductor device of claim 1 wherein:

said nano-nodules as said charge-islands coupling electrically in all three-dimensions with said intermediate region along said insulating trench.

3. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands coupling electrically with said intermediate region for distributing a voltage with a linearly graded drop along a depth of said insulating trench.

4. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nano-crystals in an oxide matrix.

5. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising implanted metal particles in an oxide matrix.

6. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated conductor or semiconductor particles in an oxide matrix.

7. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated silicon particles in an oxide matrix.

8. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising large silicon grains generated from annealed polysilicon.

9. The semiconductor device of claim 1 wherein:

said insulating trench is disposed within an active cell of said semiconductor device.

10. The semiconductor device of claim 1 wherein:

said insulating trench is disposed within an active cell between body regions of said semiconductor device.

11. The semiconductor device of claim 1 wherein:

said insulating trench is disposed within a body region of an active cell of said semiconductor device.

12. The semiconductor device of claim 1 wherein:

said intermediate region further comprising multiple epitaxial regions.

13. The semiconductor device of claim 1 wherein:

said intermediate region further comprising multiple epitaxial regions with a gradually increasing doping concentration from said bottom region toward said top region.

14. The semiconductor device of claim 1 further comprising:

a vertical FET (field effect transistor) device.

15. The semiconductor device of claim 1 further comprising:

a vertical MOSFET (metal oxide semiconductor field effect transistor) device.

16. The semiconductor device of claim 1 further comprising:

a vertical JFET (junction field effect transistor) device.

17. The semiconductor device of claim 1 further comprising:

a vertical SiT (static induction transistor) device.

18. The semiconductor device of claim 1 further comprising:

a vertical iGBT (insulated gate bipolar transistor) device.

19. The semiconductor device of claim 1 further comprising:

a bipolar device.

20. The semiconductor device of claim 1 further comprising:

a Schottky diode.

21. The semiconductor device of claim 1 further comprising:

a junction diode.

22. The semiconductor device of claim 1 further comprising:

a BJT (bipolar junction transistor) device.

23. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated silicon particles or grains in an oxide matrix.

24. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated silicon particles or grains in an oxide matrix formed by annealing of a silicon rich layer at a temperature higher than 1000 degrees Celsius.

25. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated silicon particles or grains in an insulator matrix.

26. The semiconductor device of claim 1 wherein:

said nano-nodules as charge-islands further comprising nucleated silicon particles or grains in an insulator matrix composed of an insulator comprising a silicon nitride, a silicon oxynitride or a silicon dioxide.

27. A method for manufacturing a semiconductor device comprising:

forming an insulation trench extending from a top region through an intermediate region toward a bottom region to provide a controllable current path traversing through said intermediate region;

filling said insulating trench with randomly and substantially uniformly distributed nano-nodules as charge-islands for electrically coupling with said intermediate region for continuously and uniformly distributing a voltage drop through said current path.

28. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing and a silicon rich oxide and annealing said silicon rich oxide to precipitate nano-particles.

29. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing and a Ge rich oxide and annealing said Ge rich oxide to precipitate nano-particles.

30. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of filling said insulating trench with a dielectric and implanting Si ions into said dielectric in said insulating trench followed by an annealing process.

31. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of filling said insulating trench with a dielectric and implanting Ge ions into said dielectric in said insulating trench followed by an annealing process.

32. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of filling said insulating trench with a dielectric and implanting semiconductor ions into said dielectric in said insulating trench followed by an annealing process.

33. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising a step of depositing semiconductor nano-crystals with oxide shells by applying an aerosol process.

34. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing a conductive material into said insulating trench followed by inducing a nucleation on said conductive material.

35. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing a semiconductor material into said insulating trench followed by inducing a nucleation on said semiconductor material to produce grains in said semiconductor material as said nano-nodules.

36. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing a silicon into said insulating trench followed by inducing a nucleation on said silicon to produce grains in said silicon as said nano-nodules.

37. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing a polysilicon into said insulating trench followed by steps of doping and annealing of said polysilicon in said insulating trench for inducing to produce grains in said polysilicon as said nano-nodules.

38. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising a step of filling said insulating trench with embedded semiconductor nodules.

39. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of filling said insulating trench with a dielectric material followed by applying an annealing process to said dielectric material filling in said insulating trench.

40. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing seed layers in said insulating trench followed by applying a grain formation process to form said nano-nodules in said insulating trench.

41. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing silicon in said insulating trench followed by applying a grain formation oxidation process to form separated grains as said nano-nodules in said insulating trench.

42. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of depositing a polysilicon in said insulating trench followed by applying a nucleating process to form separated silicon grains as said nano-nodules in said insulating trench.

43. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising a step of filling said insulating trench with aerosol silicon nano-crystals as said nano-nodules in said insulating trench.

44. The method of claim 27 wherein:

said step of filling said insulating trench with said distributed nano-nodules further comprising steps of applying a chemical vapor deposition (CVD) process with alternating gas types and ration to deposit multiple layer structure of SiOx/SiO2/SiOx/SiO2 with insulating between said SiOx layers followed by an annealing process to form silicon nano-crystals as said nano-nodules in said insulating trench.

45. A semiconductor device comprising:

a top region and a bottom region with an intermediate region disposed between said top region and said bottom region;

a controllable current path traversing through said intermediate region; and

a trench with padded with insulation layer on sidewalls extended from said top region through said intermediate region toward said bottom region wherein said insulating trench comprising randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below said trench for electrically coupling with said intermediate region for continuously and uniformly distributing a voltage drop through said current path.