METHOD AND DEVICE FOR DETERMINING AN OPERATIONAL LIFETIME OF AN INTEGRATED CIRCUIT DEVICE

• US 20080174329A1
• Filed: 01/18/2007
• Published: 07/24/2008
• Est. Priority Date: 01/18/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Su, Michael Zhuoying, Papageorgiou, Vassilios, Ramirez, Amado
• Granted Patent: US 7,616,021 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

Claims

1. A method comprising:

applying a test electrical bias to a degradable test structure of an integrated circuit device via an external interface pin of the integrated circuit device;

determining a degradable characteristic of the degradable test structure in response to the application of the test electrical bias to the degradable test structure; and

determining an estimated cumulative duration for which the integrated circuit device has been in operation based on the degradable characteristic.

2. The method of claim 1, further comprising:

applying an operational electrical bias to the degradable test structure when the integrated circuit device is operational.

3. The method of claim 1, further comprising:

determining a power mode of an operation of the integrated circuit device; and

wherein a magnitude of the operational electrical bias is based on the power mode for the operation of the integrated circuit.

4. The method of claim 1, wherein the degradable resistive structure comprises a metal comb structure.

5. The method of claim 1, wherein the degradable test structure comprises a via structure.

6. The method of claim 1, wherein determining a representative operational lifetime of the integrated circuit device comprises comparing the degradable characteristics to a modeled relationship between the degradable characteristic and a representative operational lifetime.

7. The method of claim 1, further comprising:

determining a warranty status of the integrated circuit device based on the estimated cumulative duration.

8. An integrated circuit device comprising:

a degradable test structure;

a first external interface pin and a second external interface pin;

a first conductive path coupling a first node of the degradable test structure and the first external interface pin; and

a second conductive path coupling a second node of the degradable test structure and the second external interface pin.

9. The integrated circuit device of claim 8, wherein the degradable test structure comprises a metal comb structure.

10. The integrated circuit device of claim 9, wherein the metal comb structure comprises a multiple-layer metal comb structure.

11. The integrated circuit device of claim 8, wherein the degradable test structure comprises:

a first conductive structure disposed at a first die layer of the integrated circuit device and coupled to the first conductive path;

a second conductive structure disposed at a second die layer of the integrated circuit device and coupled to the second conductive path; and

a via coupled to and disposed between the first conductive structure and the second conductive structure.

12. The integrated circuit device of claim 8, further comprising:

a resistance structure having an adjustable resistance; and

wherein the first node is coupled to the first external interface pin via the resistance structure.

13. The integrated circuit device of claim 12, wherein the resistance structure comprises a plurality of fuses.

14. The integrated circuit device of claim 12, further comprising:

control logic configured to adjust the adjustable resistance of the resistance structure based on a power mode of an operation of the integrated circuit device.

15. A system comprising:

an integrated circuit device comprising;

a non-volatile memory device;

a counter comprising an input configured to receive a first clock signal and an output to provide a count value;

control logic configured to store the count value of the counter in the non-volatile memory; and

means for accessing the count value from the non-volatile memory external from the integrated circuit device.

16. The system of claim 15, wherein the integrated circuit device further comprises:

a backup power component configured to provide power to the non-volatile memory device, the control logic and the counter in response to an operational failure of the integrated circuit device.

17. The system of claim 15, wherein the integrated circuit device further comprises:

a frequency divider having an input to receive a second clock signal and an output coupled to the input of the counter to provide the first clock signal; and

mode control logic configured to control a frequency division ratio of the frequency divider based on a power mode of an operation of the integrated circuit device.

18. The system of claim 15, further comprising:

a test apparatus the test apparatus configured to obtain the count value stored in the non-volatile memory device via the means for accessing the non-volatile memory external from the integrated circuit device and determine an estimated cumulative duration for which the integrated circuit device has been in operation based on the count value.

19. The system of claim 15, wherein the means for accessing the non-volatile memory external from the integrated circuit device comprises an external interface pin coupled to the non-volatile memory.

20. The system of claim 15, wherein the means for accessing the non-volatile memory external from the integrated circuit device comprises a wireless interface.