DECENTRALIZED RADIO FREQUENCY IDENTIFICATION SYSTEM

• US 20080174410A1
• Filed: 01/08/2008
• Published: 07/24/2008
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Curators of the University of Missouri (University of Missouri)
• Original Assignee: Curators of the University of Missouri (University of Missouri)
• Inventors: Ramachandran, Anil, Sarangapani, Jagannathan, Saygin, Can, Cha, Kainan
• Granted Patent: US 8,143,996 B2
• Time in Patent Office: Days
• US Class Current: 340/10.4
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10217 parameter settings controlling the transmission power of the interrogator
• CPC Class Codes: G06K 7/10356 using a plurality of antennas, e.g. configurations including means to resolve interference between the plurality of antennas

Abstract

A decentralized RFID system and method provides a decentralized power control scheme for adaptively adjusting the power of a RFID reader in a network of readers communicating with an RFID tag. The transmission power of each reader in a dense network environment is controlled as a function of interference sensed from other readers in the network and a current SNR (SNR) of a backscatter signal received from the tag. If the current SNR is above a required SNR, transmission power of the reader is reduced, which results in lower interference for other RFID readers. Similarly, if the expected SNR is below the required threshold, power is increased sufficiently to ensure that the target or required SNR is achieved.

Claims

1. A decentralized RFID system comprising:

a first reader for transmitting a first carrier signal;

a second reader for transmitting a second carrier signal;

a tag for receiving the first and second carrier signals, wherein the tag is responsive to the first carrier signal to transmit a first backscatter signal, and wherein the tag is responsive to the second carrier signal to transmit a second backscatter signal; and

wherein the first and second readers further include a first processor and a second processors, respectively, and wherein the first processor measures a degree of interference from the second carrier signal, and wherein the second processor measures a degree of interference from the first carrier signal, the first and second processor each executing instructions for adjusting a respective transmission power level of the first and second carrier signals being transmitted from the first and second readers, respectively, as a function of the measured degree of interference.

2. The decentralized RFID system of claim 1, wherein the first and second processors execute instructions to calculate a new transmission power level of the corresponding first and second readers based on the degree of interference measured at the first and second readers and an estimated channel behavior at a next time step.

3. The decentralized RFID system of claim 2, wherein the new transmission power level is controlled such that an expected signal-to-noise ratio reaches a signal-to-noise ratio required for a desired reading range for the first and second readers.

4. The decentralized RFID system of claim 3, wherein if the expected signal-to-noise ratio is above the required signal-to-noise ratio required for a desired reading range, the transmission power of one of the first or second readers is reduced.

5. The decentralized RFID system of claim 3, wherein if the expected signal- to-noise ratio is below the required signal-to-noise ration required for a desired read range, the transmission power of one of the first or second readers is increased.

6. The decentralized RFID system of claim 2, wherein a selective back-off scheme is employed to ensure that both the first and second readers achieve a respective desired read range.

7. The decentralized RFID system of claim 6, wherein the selective back-off scheme uses a quality control parameter based on the percentage of time the first and second readers achieve a respective desired read range.

8. The decentralized RFID system of claim 7, Wherein the selective back-off scheme uses a logarithm function of the percentage of time a respective first or second reader has attained the required signal-to-noise ratio using the following algorithm:

τ

_w=10·

[log₁₀(ρ

+0.01)+2]

wherein ρ

is the percentage of time a respective first and second reader has attained the required signal-to-noise ratio.

9. The decentralized RFID system of claim 2, wherein the new power transmission for the first and second readers is calculated based on an embedded channel prediction to account for the time-varying facing channel state for a next cycle.

10. The decentralized RFID system of claim 1, wherein the first and second processors execute instructions to select a new transmission power level of the corresponding first and second readers from a specified probability distribution based on the degree of interference measured at the respective first and second readers.

11. A decentralized RFID system comprising:

a plurality of readers, each of the plurality of readers capable of transmitting a respective carrier signal;

at least one tag in operative communication with one or more of the plurality of readers for receiving one or more of the respective carrier signals from the plurality of readers; and

wherein each of the the plurality of readers includes a module having an algorithm for adjusting a respective power output for each of the plurality of readers as a function of a respective measured interference at that respective plurality of readers in order to achieve a predetermined signal-to-noise ratio (SNR).

12. A method for adjusting a transmission power level of at least one of a plurality of radio frequency identification (RFID) readers included in a network of RFID readers, the method comprising:

transmitting a first carrier signal from a first RFID reader included in the network of RFID readers and transmitting a second carrier signal from a second RFID reader of the network included in RFID readers, wherein the first RFID reader operates at a first power level, and wherein the second RFID reader operates at a second power level;

receiving the first and second carrier signals at a RFID tag;

generating, at the RFID tag, a first backscatter signal in response to the first carrier signal and a second backscatter in response to the second carrier signal;

processing the second carrier signal at the first RFID reader to measure a first level of interference and processing the first carrier signal at the second RFID reader to measure a second interference level, the first level of interference corresponding to an amount of interference from the second carrier signal, and the second level of interference corresponding to an amount of interference from the first carrier signal; and

adjusting the first power level of the first RFID reader as a function of the first level of inference and adjusting the second power level of the second RFID reader as a function of the second level of interference.

13. The method of claim 12, further including measuring an interference level from the second carrier signal from the second RFID reader as a function of a calculated current signal-to-noise value and an expected signal-to-noise value, the expected signal-to-noise value being retrieved from a memory and corresponding to signal-to-noise value a required to achieve a desired read and bit error rate;

14. A processor having executable components for adjusting a transmission power level of at least one radio frequency identification (RFID) reader in a decentralized RFID system, the decentralized RFID system comprising a first reader to transmit a first carrier signal at a first power level;

a second reader to transmit a second carrier signal at a second power level, and a tag to receive the first and second carrier signals and to generate, at the tag, a first backscatter signal in response to the first carrier signal and a second backscatter in response to the second carrier signal, the processor comprising;

a power update component to determine a current transmission power corresponding to the first carrel signal and to calculate a current signal-to-noise ratio value based on the current transmission power level and signal-to-noise ratio data retrieved from a memory;

a signal-to-noise ratio comparator component to compare the current signal-to-noise value to a required signal-to-noise value retrieved from the memory and to generate a first output signal as a function of the comparison;

a percentage signal-to-noise ratio achieved component to calculate a back-off parameter as a function of the first output signal, wherein the back-off parameter corresponds to a percentage of time the required signal-to-noise ratio is achieved;

wherein the power update component is further responsive to the first generated output signal to calculate a new transmission power required to achieve the desired signal-to-noise ratio;

a limiter component to receive the new transmission power and to limit the new calculated transmission power within a specified transmission power range;

a power comparator component to receive the new transmission power thru the limiter component, to compare the new transmission power to a maximum transmission power value retrieved from the memory, and to generate a second output signal as a function of the comparison; and

a selective back-off component is responsive to the second output signal from the power comparator component, the new transmission power received thru the limiter, and the back-off parameter from the percentage signal-to-noise ratio achieved component to determine whether to operate the first reader in a normal mode or a selective back-off mode, wherein the first reader outputs the new transmission power for generating the first carrier signal during normal mode, and wherein the first reader waits for a determined time period before outputting the new transmission power during the back-off mode.

15. The processor of claim 14, wherein the selective back-off component determines that the first reader is in normal mode when the calculated new power is less than the maximum transmission power, and wherein the selective back-off component determines that the first reader is in the selective back-off mode when the calculated new power is greater than maximum transmission power value.

16. The processor of claim 14, wherein the second generated output signal has a low output signal when the new transmission power is less than the maximum transmission power, and wherein the second generated has a high output signal when the new transmission power greater than the maximum transmission power.

17. The processor of claim 14, wherein the power update component further estimates a channel signal-to-noise ratio value at a next time step and calculates the new transmission power level as a function of the channel estimate.

18. The processor of claim 17 wherein the power update component estimates the channel signal-to-noise ratio value with the following algorithm:

19. The processor of claim 14, wherein the signal-to-noise comparator component generates the first output signal having a first magnitude when the current signal-to-noise value is less than a required signal-to-noise value, and wherein the signal-to-noise ratio comparator component generates the first output signal having a second magnitude when the calculated current signal-to-noise ratio is equal to the required signal-to-noise ratio.