PFET NONVOLATILE MEMORY

• US 20080175050A1
• Filed: 10/02/2007
• Published: 07/24/2008
• Est. Priority Date: 05/05/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: PESAVENTO, ALBERTO, Hyde, John D.
• Granted Patent: US 8,111,558 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability

Abstract

A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

Claims

1. A nonvolatile memory cell, comprising:

a first floating gate;

a first pFET having gate, source and drain terminals, said gate terminal coupled to said first floating gate;

a first control capacitor structure having a first terminal coupled to a first voltage supply node and a second terminal coupled to said first floating gate; and

a first tunneling capacitor structure having a first terminal coupled to a second voltage supply node and a second terminal coupled to said first floating gate.

2. A method for programming memory cells in an array of differential pFET nonvolatile memory cells arranged in rows and columns of cells, the method comprising:

providing row control signals to the cells of a given row, the row control signals including tunneling control signals, row enable signals and row select signals; and

providing column control signals to the cells of a given column, the column control signals including a first and a second data signal for each cell, wherein each cell includes a first floating gate and a second floating gate, the first floating gate being coupled to a gate of a first pFET readout transistor and to a first terminal of a first control capacitor structure and to a first terminal of a first tunneling capacitor structure and the second floating gate being coupled to a gate of a second pFET readout transistor and to a first terminal of a second control capacitor structure and to a first terminal of a second tunneling capacitor structure, drains of the first and second readout transistor being selectively coupled in response to the row select signals to current sense amplifiers associated with each column of cells.

3. The method of claim 2, in which

the tunneling control signals are voltage signals sufficient to cause Fowler-Nordheim tunneling across a dielectric insulating the first and second floating gates.

4. An apparatus for programming memory cells in an array of differential pFET nonvolatile memory cells arranged in rows and columns of cells, the apparatus comprising:

means for providing row control signals to the cells of a given row, the row control signals including tunneling control signals, row enable signals and row select signals; and

means for providing column control signals to the cells of a given column, the column control signals including a first and a second data signal for each cell, wherein each cell includes a first floating gate and a second floating gate, the first floating gate being coupled to a gate of a first pFET readout transistor and to a first terminal of a first control capacitor structure and to a first terminal of a first tunneling capacitor structure and the second floating gate being coupled to a gate of a second pFET readout transistor and to a first terminal of a second control capacitor structure and to a first terminal of a second tunneling capacitor structure, drains of the first and second readout transistor being selectively coupled in response to row select signals to current sense amplifiers associated with each said column of cells.

5. The apparatus of claim 4, in which

said tunneling control signals are voltage signals sufficient to cause Fowler-Nordheim tunneling across a dielectric insulating the first and second floating gates.