Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes

• US 20080175071A1
• Filed: 03/28/2008
• Published: 07/24/2008
• Est. Priority Date: 07/20/2001
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Chang-sik, Kyung, Kye-hyun, Lee, Kee-hoon
• Application Number:
  US12/058,441
• Publication Number:
  US 20080175071A1
• Time in Patent Office: Days
• US Class Current: 365/189.04
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Claims

1. A method of operating a memory system comprising a plurality of memory devices coupled to a command address bus, the method comprising:

setting a first memory device of the plurality of memory devices to a first operating mode;

setting a second memory device of the plurality of memory devices to a second operating mode different than the first operating mode;

setting a third memory device of the plurality of memory devices to a third operating mode different than at least one of the first and/or second operating modes; and

performing a read/write operation responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation, so that the second memory device operates according to the second operating mode during the read/write operation, and so that the third memory device operates according to the third operating mode during the read/write operation.

2. A method according to claim 1 wherein setting the first memory device to the first operating mode comprises providing a first mode set command address signal to the plurality of memory devices and providing an identification signal to the first memory device without providing an identification signal to the second and third memory devices.

3. A method according to claim 2 wherein setting the second memory device to the second operating mode comprises providing a second mode set command address signal to the plurality of memory devices and providing an identification signal to the second memory device without providing an identification signal to the first and third memory devices.

4. A method according to claim 3 wherein providing the identification signals to the first and second memory devices comprises providing the identification signals to one of a data pin, a data mask pin, and/or a data strobe pin of the respective memory device.

5. A method according to claim 2 wherein the first mode set command address signal comprises a Mode Register Set (MRS) command.

6. A method according to claim 1 wherein the first operating mode comprises a refresh mode and wherein the second operating mode comprises a deep power down mode.

7. A method according to claim 1 wherein performing the read/write operation comprises performing the read/write operation responsive to the read/write command address signal and responsive to a clock signal provided over the command address bus to the plurality of memory devices.

8. A method according to claim 1 wherein the third operating mode is different than the first and second operating modes.