CLOCK GENERATING APPARATUS AND CLOCK GENERATING METHOD

• US 20080175342A1
• Filed: 01/14/2008
• Published: 07/24/2008
• Est. Priority Date: 01/16/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Jang, Kyungwoon
• Granted Patent: US 7,705,652 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H04N 21/236 Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream multiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/8547 involving timestamps for synchronizing content
• CPC Class Codes: H04N 7/56 Synchronising systems therefor

Abstract

A clock generating apparatus has an integral ratio divider for, according to frequency-dividing parameters for generating a second clock signal including a second frequency by using a first clock signal including a first frequency, outputting the second clock signal, and a frequency-dividing parameter generating portion for comparing program clock reference inputted from outside with an STC value based on the second clock signal and outputting the frequency-dividing parameters so as to converge a discrepancy between the program clock reference and the STC value within a predetermined range, and wherein the frequency-dividing parameter generating portion generates new frequency-dividing parameters each time the program clock reference is inputted from outside.

Claims

1. A clock generating apparatus comprising:

an integral ratio divider for, according to frequency-dividing parameters for generating a second clock signal including a second frequency by using a first clock signal including a first frequency, outputting the second clock signal; and

a frequency-dividing parameter generating portion for comparing program clock reference inputted from outside with an STC value based on the second clock signal and outputting the frequency-dividing parameters so as to converge a discrepancy between the program clock reference and the STC value within a predetermined range, and wherein;

the frequency-dividing parameter generating portion generates new frequency-dividing parameters each time the program clock reference is inputted from outside.

2. The clock generating apparatus according to claim 1, wherein a difference between the program clock reference and the STC value is used as the discrepancy between the program clock reference and the STC value.

3. The clock generating apparatus according to claim 1, wherein the frequency-dividing parameters are a value indicating the number of times of outputting per unit time a frequency of frequency-dividing the first clock signal a first number of times and a value indicating the number of times of outputting per unit time a frequency of frequency-dividing the first clock signal a second number of times, and the two values are fine-tunable values.

4. The clock generating apparatus according to claim 3, wherein the first number of times is a number larger than the second number of times by 1.

5. A clock generating apparatus comprising:

an integral ratio divider for, provided with a first clock signal of a first frequency and frequency-dividing parameters, outputting a second clock signal of a second frequency by combining P (P is an integer of 1 or more) frequency dividing of the first clock signal with P+1 frequency dividing at a ratio based on the frequency-dividing parameters;

a counter for having the second clock signal inputted and generating and outputting a count value based on the second clock signal;

a subtracter for, provided with a PCR value included in program clock reference and the count value, calculating a difference between the PCR value and an STC value based on the count value and outputting it as a difference value; and

a frequency-dividing parameter generating portion for having the difference value, a previous difference value which is the difference value outputted from the subtracter last time and previous frequency-dividing parameters which are the frequency-dividing parameters outputted last time inputted, comparing the difference value with the previous difference value and adjusting the previous frequency-dividing parameters based on a comparison result so as to output the frequency-dividing parameters.

6. The clock generating apparatus according to claim 5, further comprising:

a storage portion for storing the difference value outputted from the subtracter and the frequency-dividing parameters outputted from the frequency-dividing parameter generating portion and outputting them as the previous difference value and the previous frequency-dividing parameters after a predetermined time.

7. The clock generating apparatus according to claim 5, wherein the difference value is converged within a predetermined range.

8. The clock generating apparatus according to claim 5, wherein the frequency-dividing parameter generating portion outputs the same values as the previous frequency-dividing parameters as the frequency-dividing parameters in the case where a sign of the difference value is the same as the sign of the previous difference value and an absolute value of the difference value is equal to or less than the absolute value of the previous difference value.

9. The clock generating apparatus according to claim 5, wherein the subtracter sets the PCR value provided after a predetermined time as a counter value of the counter in the case where the difference value is larger than a predetermined error determination value.

10. A clock generating method comprising:

generating and outputting a second clock signal including a second frequency by combining P (P is an integer of 1 or more) frequency dividing and P+1 frequency dividing of a first clock signal including a first frequency at a ratio based on frequency-dividing parameters;

counting the second clock signal and outputting a count value;

calculating a difference between a PCR value included in program clock reference and an STC value based on the count value and outputting a difference value; and

generating and outputting the frequency-dividing parameters based on transition of the difference value.

11. The clock generating method according to claim 10, wherein the difference value is converged within a predetermined range.