Low Jitter Communication System

• US 20080175344A1
• Filed: 12/20/2007
• Published: 07/24/2008
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Tolfi, Thomas H., Menolfi, Christian I., Schmatz, Martin Leo
• Granted Patent: US 8,170,157 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by means of the delayed jitter signal.

Claims

1. A communication system comprising:

a transmitter;

a receiver, and

a clock channel and a data channel coupling the transmitter and the receiver, wherein the clock channel is shorter than the data channel, and

wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by means of the delayed jitter signal.

2. The communication system according to claim 1, wherein the extracted jitter signal is delayed by the propagation delay time difference of the clock channel and the data channel.

3. The communication system according to claim 1, wherein one or more parts of the jitter spectrum are extracted from the clock channel signal as a jitter signal and wherein the receiver clock signal is generated by means of adding the delayed parts of the jitter spectrum to the difference signal of the clock channel signal and the non-delayed extracted jitter signal.

4. The communication system according to claim 3, wherein a high frequency spectrum is extracted from the clock channel signal as a jitter signal by means of a high pass filter.

5. The communication system according to claim 1, wherein substantially the whole jitter spectrum is extracted from the clock channel signal as a jitter signal and wherein the receiver clock signal is generated by means of adding the extracted jitter spectrum to a substantially clean clock reference signal.

6. The communication system according to claim 1, wherein the high pass filter is implemented by means of a phase locked loop comprising a phase detector, a loop filter and a voltage controlled oscillator, wherein the phase detector is provided for receiving the clock channel signal and for delivering the extracted jitter signal as an output signal.

7. The communication system according to claim 6, wherein the difference signal of the clock channel signal and the non-delayed extracted jitter signal is derived from the voltage controlled oscillator of the phase locked loop.

8. The communication system according to claim 4, wherein the cut-off frequency of the high pass filter is selected in dependence on the propagation delay time difference between the clock channel and the data channel.

9. The communication system according to claim 1, wherein the delay circuit comprises a coarse delay unit for performing a coarse delay of the extracted jitter signal.

10. The communication system according to claim 1, wherein the delay circuit comprises a controllable delay buffer for adding the extracted and delayed jitter signal to the difference signal or the substantially clean reference signal.

11. The communication system according to claim 6, wherein the delay circuit comprises an injection unit for injecting the extracted and delayed jitter signal to the control voltage of the voltage controlled oscillator.

12. A receiver for a source-synchronous communication system, wherein the receiver comprises a delay circuit and wherein the delay circuit is provided for

extracting a jitter signal from a received clock channel signal,

delaying the extracted jitter signal,

generating a receiver clock signal for the receiver by means of the delayed jitter signal.

13. A method for synchronizing a clock channel signal and a data channel signal of a source-synchronous communication channel, wherein the clock channel and the data channel comprise a propagation delay time difference, the method comprising the steps of:

receiving the clock channel signal and the data channel signal,

extracting a jitter signal from the received clock channel signal,

delaying the extracted jitter signal,

generating a receiver clock signal by means of the delayed jitter signal.