Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count

• US 20080176343A1
• Filed: 01/22/2007
• Published: 07/24/2008
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yi-Kan, Chang, Gwan Sin, Hou, Cliff
• Granted Patent: US 7,801,717 B2
• Time in Patent Office: Days
• US Class Current: 438/5
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

Claims

1. A method comprising:

providing a circuit pattern;

generating a density report for the circuit pattern that identifies a feasible area for dummy insertion;

simulating a planarization process with the density report and identifying a hot spot on the circuit pattern;

inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly; and

simulating, after the inserting, the planarization process with the adjusted density until the hot spot is eliminated.

2. The method of claim 1, wherein the providing includes providing the circuit pattern in a computer aided design format.

3. The method of claim 2, wherein the providing includes providing the circuit pattern in GDS format.

4. The method of claim 1, wherein the providing includes configuring the circuit pattern to include a plurality of metal levels.

5. The method of claim 1, wherein the generating includes dividing the circuit layout into a plurality of regions and determining a local density for each of the plurality of regions in a software environment.

6. The method of claim 5, wherein the software environment includes a design rule check (DRC) tool.

7. The method of claim 1, wherein the simulating includes running a virtual chemical mechanical polishing (VCMP) simulator to generate a thickness and topography report for the plurality of regions.

8. The method of claim 7, wherein the identifying includes identifying the hot spot where a thickness deviation between neighboring regions is greater than a minimum thickness.

9. A method comprising:

providing a circuit layout;

generating a density report for the circuit layout to identify an area for dummy insertion;

simulating a first planarization process that implements a first density insertion for inserting dummy patterns within the area and a second planarization process that implements a second density insertion for inserting dummy patterns within the area; and

determining an optimal dummy insertion for the circuit layout by comparing a first thickness report from the first planarization process with a second thickness report from the second planarization process to identify a hot spot and a cold spot.

10. The method of claim 9, wherein the generating includes dividing the circuit layout into a plurality of grids, wherein each grid has a local density associated with it.

11. The method of claim 10, wherein the generating includes running a design rule check (DRC) on the plurality of grids to identify the area and its density for dummy insertion.

12. The method of claim 9, wherein the simulating includes running a virtual chemical mechanical polishing (VCMP) simulator.

13. The method of claim 9, wherein the simulating includes configuring the first density insertion to include a minimal density insertion.

14. The method of claim 13, wherein the simulating includes configuring the second density insertion to include a target density insertion.

15. The method of claim 9, wherein the determining includes identifying the cold spot for removing dummy patterns within the area, the cold spot is where a thickness deviation between a grid from the first simulated planarization process and that same grid from the second simulated planarization process is less than a minimum thickness.

16. The method of claim 15, wherein the determining includes identifying the hot spot for adding dummy patterns within the area, the hot spot is where a thickness deviation between neighboring grids is greater than a minimum thickness.

17. The method of claim 15, wherein the determining includes identifying the hot spot for adding dummy patterns within the area, the hot spot is where a thickness deviation between a grid from the first thickness report and the same grid from the second thickness report is greater than a minimum thickness.

18. The method of claim 9, further comprising generating a final circuit layout with the optimal dummy insertion.

19. A semiconductor device comprising:

a circuit layout having a plurality of regions, wherein each region has a local density associated with it;

an area within the circuit layout that is available for dummy insertion; and

an optimal dummy insertion formed within the area, wherein the optimal dummy insertion is configured by comparing a first simulated planarization process implementing a first density insertion with a second simulated planarization process implementing a second density insertion to identify a hot spot and a cold spot.

20. The device of claim 19, wherein the first density insertion includes a minimal density insertion.

21. The device of claim 20, wherein the second density insertion includes a target density insertion.

22. The device of claim 21, wherein the optimal dummy insertion includes removing dummy patterns in the cold spot, the cold spot is where a thickness deviation between a region from the first simulated planarization process and that same region from the second simulated planarization process is less than a minimum thickness.

23. The device of claim 22, wherein the optimal dummy insertion includes adding dummy patterns in the hot spot, the hot spot is where a thickness deviation between neighboring regions is greater than a minimum thickness.

24. The device of claim 22, wherein the optimal dummy insertion includes adding dummy patterns in the hot spot, the hot spot is where a thickness deviation between a region from the first simulated planarization process and that same region from the second simulated planarization process is greater than a minimum thickness.