STRESS FREE PACKAGE AND LAMINATE-BASED ISOLATOR PACKAGE

• US 20080176362A1
• Filed: 01/24/2007
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Sengupta, Dipak, Goida, Thomas
• Granted Patent: US 7,871,865 B2
• Time in Patent Office: Days
• US Class Current: 438/123
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83051 : Forming additional members, e.g. dam structures
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF-based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.

Claims

1. A window frame ACF-based stress isolation method for a lead frame package comprising:

(a) applying an ACF layer on a polyimide layer on lead frame die attach paddle; and

(b) bonding a die to said applied ACF layer,

said ACF layer providing stress isolation to said die by forming a gap in between said die and said polyimide layer.

2. A multi-tier ACF-based stress isolation method for a lead frame package comprising:

(a) applying a multi-tier ACF film with a notch on a polyimide layer on lead frame die attach paddle; and

(b) bonding a die to said applied multi-tier ACF film with said notch, said bonding done such that said notch is disposed between said die and said polyimide layer,

said multi-tier ACF film providing stress isolation to said die via said notch.

3. A window frame ACF-based stress isolation method for a BGA or LGA package comprising:

(a) applying an ACF layer on a BGA or LGA substrate; and

(b) bonding a die to said applied ACF layer,

said ACF layer providing stress isolation to said die by forming a gap in between said die and said BGA or LGA substrate.

4. A window frame ACF-based stress isolation method for a BGA or LGA package comprising:

(a) applying an multi-tier ACF film with a notch on a BGA or LGA substrate; and

(b) bonding a die to said applied ACF layer, said bonding done such that said notch is disposed between said die and said BGA or LGA substrate,

said mutli-tier ACF film providing stress isolation to said die via said notch.

5. A window-frame ACF-based isolation method for magnetic coupling in a lead frame package comprising:

(a) applying an ACF layer on a polyimide layer on lead frame die attach paddle, said ACF layer having a first metal trace; and

(b) bonding a die to said applied ACF layer, said die having a second metal trace,

said ACF layer isolating said first and second metal traces, said isolated first and second metal traces providing magnetic coupling.

6. A window-frame ACF-based isolation method for magnetic coupling in a BGA or LGA package comprising:

(a) applying an ACF layer on a BGA or LGA substrate, said ACF layer having a first metal trace; and

(b) bonding a die to said applied ACF layer, said die having a second metal trace,

said ACF layer isolating said first and second metal traces, said isolated first and second metal traces providing magnetic coupling.

9. The method of claim 6, wherein said perimeter is formed of polymer.

10. The method of claim 9, wherein said polymer perimeter is formed via screen printing.

7. A method to reduce stress in a semiconductor package comprising:

(a) selecting a stress sensitive area on a semiconductor die;

(b) depositing a perimeter around said stress sensitive area on the semiconductor die; and

(c) forming an air gap by contacting said semiconductor die having said deposited perimeter with a lead frame,

wherein the formed air gap prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.

8. The method of claim 7, wherein, prior to (c), said method further comprises the step of depositing another perimeter around said lead frame.

11. A method to reduce stress in a semiconductor package comprising:

(a) selecting a stress sensitive area on a semiconductor die;

(b) depositing a perimeter on a lead frame; and

(c) contacting said lead frame having said perimeter with said semiconductor die,

wherein said perimeter forms an air gap and prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.

12. The method of claim 11, wherein, prior to (c), said method further comprises the step of depositing another perimeter around said stress sensitive area of said semiconductor die.

13. The method of claim 11, wherein said perimeter is formed of polymer.

14. A method teaching to produce a laminate that aids in reducing package stress comprising:

identifying known dimensions associated with a specific semiconductor die; and

depositing a perimeter on a laminate,

wherein said perimeter is dimensioned such that an air gap is formed when the specific semiconductor die of know dimensions is placed on top of said laminate.

15. The method of claim 14, wherein said perimeter is formed of polymer.

16. A method to form a stress free package comprising the steps of:

depositing a first perimeter on a laminate;

depositing a second perimeter on a semiconductor die; and

forming an air gap by placing said semiconductor die with said second perimeter on said laminate with said first perimeter,

wherein the formed air gap prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.

17. The method of claim 16, wherein said first and second perimeter are formed of polymer.

18. A method to reduce stress in a semiconductor package comprising:

(a) depositing an anisotropic conducting film (ACF) on a semiconductor die, said ACF film further containing gold stud bumps; and

(b) forming an air gap by contacting said semiconductor die having said deposited ACF film with gold stud bumps with a lead frame,

wherein the formed air gap prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.

19. A method to reduce stress in a semiconductor package comprising:

(a) depositing a continuous anisotropic conducting film (ACF) on a semiconductor die, said ACF film further having a plurality of gold stud bumps dispersed within; and

(b) contacting said semiconductor die having said deposited ACF film with gold stud bumps with a lead frame,

wherein said ACF film with gold stud bumps prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.

20. A method to reduce stress in a semiconductor package comprising:

(a) depositing a notched anisotropic conducting film (ACF) on a semiconductor die, said ACF film further containing gold stud bumps; and

(b) forming an air gap by contacting said semiconductor die having said notched ACF film with gold stud bumps with a lead frame,

wherein the formed air gap prevents underfill or molding compound from coming in contact with said stress sensitive area on the semiconductor die.