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TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS

  • US 20080177517A1
  • Filed: 03/26/2008
  • Published: 07/24/2008
  • Est. Priority Date: 02/13/2003
  • Status: Abandoned Application
First Claim
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1. A method for modeling, in a computer system, the behavior of a logical circuit block, the method comprising:

  • first calculating in said computer system a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;

    second calculating in said computer system a delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage; and

    displaying by said computer system, a result of at least one of said first and second calculating.

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