Hardware support system for accelerated disk I/O

• US 20080177925A1
• Filed: 12/28/2007
• Published: 07/24/2008
• Est. Priority Date: 12/01/2003
• Status: Active Grant

• Current Assignee: Krishnaraj S. Rao, Radoslav Danilak
• Original Assignee: Krishnaraj S. Rao, Radoslav Danilak
• Inventors: Danilak, Radoslav, Rao, Krishnaraj S.
• Granted Patent: US 8,700,808 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.

Claims

1. A disk controller for implementing efficient disk I/O for a computer system, comprising:

a bus interface for interfacing with a processor and a system memory of the computer system;

a disk I/O engine coupled to the bus interface; and

a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive, wherein the disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor, the disk I/O engine further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.

2. The disk controller of claim 1, wherein the bus interface is configured to interface with the processor and the system memory of the computer system in accordance with a hyper transport protocol.

3. The disk controller of claim 1, wherein the device interface is configured to coupled to a serial ATA interface of the disk drive.

4. The disk controller of claim 1, wherein the device interface is configured to couple to an IDE interface of the disk drive.

5. A bridge component for implementing efficient disk I/O for a computer system, comprising:

a bus interface for interfacing with a processor and a system memory of the computer system;

a disk controller for executing disk I/O transactions for the computer system, the disk controller further comprising;

a disk I/O engine coupled to the bus interface; and

a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive, wherein the disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor, the disk I/O engine further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.

6. The bridge component of claim 5, wherein at least one of the channels is a serial ATA channel.