SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE

• US 20080177928A1
• Filed: 01/23/2008
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJISAWA, Shinya, NISHIYAMA, Masuji, SUZUKI, Takahiro, HARA, Tokumasa
• Granted Patent: US 8,082,383 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory

Abstract

A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Claims

1. A semiconductor memory device comprising:

a memory cell array which includes a nonvolatile memory cell;

a power source circuit which includes a first register and generates a voltage to be used in at least any one of write, erase and read of data with respect to the memory cell;

a sense amplifier which includes a second register, reads data from the memory cell and amplifies the read data;

a control circuit which includes a third register and controls operations of the power source circuit and the sense amplifier; and

a processor which controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers, the control circuit decoding the instruction of the processor received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

2. The device according to claim 1, wherein the memory cell has a stacked gate including a charge accumulation layer and a control gate.

3. A semiconductor memory device having a first operation mode in which an operation is automatically carried out under a control of a processor and a second operation mode in which the operation is carried out independently of the control of the processor, comprising:

a memory cell array which includes a nonvolatile memory cell;

a power source circuit which generates a voltage to be used in at least any one of write, erase and read of data with respect to the memory cell;

the processor which generates a first signal on the first operation mode to control an operation of the power source circuit; and

a control circuit which includes a first register configured to hold one of the first signal and a second signal and which controls the power source circuit based on one of the first and second signals held in the first register, the second signal being a signal to boot the power source circuit, the first register holding the first signal after holding the second signal when the second operation mode is changed to the first operation mode.

4. The device according to claim 3, further comprising a switch circuit which causes the first register to hold the first signal on the first operation mode and, when the second operation mode is changed to the first operation mode, causes the first register to hold the first signal after holding the second signal.

5. The device according to claim 4, wherein the first register is in a reset state on the second operation mode, and

the switch circuit includes a selection circuit which selects the second signal when the first register is in the reset state and selects the first signal when not in the reset state;

and

an update circuit which prohibits updating of data held to the first register on the second operation mode and permits the updating on the first operation mode.

6. The device according to claim 5, further comprising an oscillation circuit which generates a clock on the first operation mode,

wherein the update circuit permits the first register to update data in response to generation of the clock when the second operation mode is changed to the first operation mode,

the first register fetches the second signal in response to the permission for the update, and

after the first register fetches the second signal, the first register fetches the first signal in response to an output of an update signal from the processor.

7. The device according to claim 3, further comprising an analyzing circuit which obtain the second signal by decoding a command externally input.

8. The device according to claim 4, wherein the first signal is a signal of (M+N) bits (M is a natural number of 1 or higher and N is a natural number of 2 or higher),

the control circuit controls the power source circuit using the N bits of the first signal on the first operation mode, and

the power source circuit changes a generated voltage to a value corresponding to a third signal input from the processor at a timing given by the M bits of the first signal on the first operation mode.

9. The device according to claim 8, wherein the power source circuit includes

a second register which, when an update signal is given from the processor, fetches the third signal;

a third register which fetches the third signal transferred from the second register in response to the value of the M bit of the first signal held in the first register; and

a voltage generating unit which generates the voltage corresponding to the third signal held in the third register.

10. The device according to claim 3, wherein the memory cell has a stacked gate including a charge accumulation layer and a control gate.

11. A semiconductor memory device in which an operation is automatically carried out under a control of a processor, comprising:

a first memory block including a plurality of nonvolatile memory cells, data held in the memory cells included in the first memory block being erased at a time.

a plurality of second memory blocks including the memory cells, data held in the memory cells included in the second memory blocks being erase at a time, the number of the memory cells included in each of the second memory blocks being smaller than that in the first memory block;

a sense amplifier which reads data from the memory cell and amplifies the data, the sense amplifier reading data from selected one of the second memory block and non-selected one of the second memory blocks continuously, when the data is read from one of the second memory block;

a verification circuit which verifies whether or not write or erase of data to the memory cell has been carried out properly using the data read by the sense amplifier, the verification circuit, when the data is read from the non-selected one of the second memory cell block, determining that the write or erase of data has been performed properly regardless of the read data; and

the processor which provides information concerning selection/non-selection of the second memory block to the verification circuit.

12. The device according to claim 11, wherein the information concerning selection/non-selection given from the processor is information indicating which of the second memory blocks has been selected, and

the verification circuit includes

a register configured to hold the information concerning selection/non-selection;

a determination circuit which determines whether or not the memory cells from which data is read by the sense amplifier is included in the selected one of the second memory blocks by using an address of the verified memory cells and the information held in the register;

a holding circuit which holds a result of verification about the data read by the sense amplifier; and

an output circuit which, when it is determined that the memory cells is included in the selected one of the second memory blocks by the determination circuit, outputs the verification result held in the holding circuit and when it is determined that the memory cell is not included in the selected one of the second memory cells, outputs data indicating that the verification has been completed properly regardless of the verification result held in the holding circuit.

13. The device according to claim 11, wherein the memory size of each of the second memory blocks is equal, and

the memory size of the first memory block is integer times the memory size of each of the second memory blocks.

14. The device according to claim 11, wherein the memory cells have a stacked gate including a charge accumulation layer and a control gate.