Defective memory block remapping method and system, and memory device and processor-based system using same

• US 20080177933A1
• Filed: 01/22/2007
• Published: 07/24/2008
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nobunaga, Dean, Li, Hanqing
• Granted Patent: US 7,743,303 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Claims

1. A method of addressing a memory device having blocks of non-volatile memory cells, the method comprising:

keeping a record of the respective addresses of all blocks of memory cells in the memory device that are non-functional;

receiving a block address corresponding to a block of the memory cells;

using the received block address as a comparison block address;

when the block address is received, comparing the comparison block address with the block addresses in the kept record, the block addresses in the kept record being compared to the comparison block address in order from a lowest address to a highest address;

for a block address in the kept record that is found by the comparison to be lower than or equal to the comparison block address, adding to the comparison block address a number corresponding to size of the non-functional block to provide an output block address; and

using the output block address to address the memory device.

2. The method of claim 1 wherein the record of the respective addresses of all blocks of memory cells in the memory device that are non-functional further contains a record of the size of each non-functional block, and wherein the act of adding to the comparison block address a number corresponding to size of the non-functional block comprises adding to the comparison block address the record of the size of the non-functional block.

3. The method of claim 1, further comprising:

if a block address in the kept record was found to be lower than or equal to the comparison block address, using the output address as a subsequent comparison block address;

compare each subsequent comparison block address with the block addresses in the kept record, and

for each block address in the kept record that is found to be lower than or equal to each subsequent comparison block address, adding the subsequent comparison block address a number corresponding to size of the non-functional block to provide an output block address; and

performing the above acts until a block address in the kept record is found to be greater than a subsequent comparison block address; and

using the output block address to address the memory device.

4. The method of claim 1 wherein the act of keeping a record of the respective addresses of all blocks of memory cells in the memory device that are non-functional comprises associating each of the addresses in the record with an index number, the index numbers being assigned to the addresses in order from a lowest index number associated with the lowest address to a highest index number associated with the highest address.

5. The method of claim 4 wherein the act of comparing the comparison block address with the block addresses in the kept record comprises:

successively incrementing the index number from the lowest index number to the highest index number; and

using the index numbers to obtain the respective addresses from the kept record; and

comparing the comparison block address with each of the obtained addresses.

6. A method of addressing a memory device having blocks of non-volatile memory cells, the method comprising:

keeping a record of the respective block addresses of all blocks of memory cells in the memory device that are non-functional;

receiving a block address corresponding to a block of the memory cells;

providing an output block address corresponding to the sum of the received block address and the sum of addresses corresponding to the sizes of any and all non-functional blocks of memory cells having respective block addresses in the kept record that are lower than or equal to the output block address; and

using the output block address to address the memory device.

7. The method of claim 6 wherein the act of providing the output block address comprises:

comparing the received block address with the block addresses in the kept record, the block addresses being compared in order from a lowest block address to a highest block address; and

if a block address in the kept record that is found by the comparison to be lower than or equal to the received block address, adding to the received address an address corresponding to size of the block corresponding to the block address.

8. The method of claim 6 wherein the act of keeping a record of the respective block addresses of all blocks of memory cells in the memory device that are non-functional comprises keeping the record of the respective block addresses in order from a lowest block address to a highest block address.

9. The method of claim 6 wherein the act of keeping a record of the respective addresses of all blocks of memory cells in the memory device that are non-functional comprises associating each of the addresses in the record with an index number, the index numbers being assigned to the addresses in order from a lowest index number associated with the lowest address to a highest index number associated with the highest address.

10. The method of claim 6 wherein the record of the respective addresses of all blocks of memory cells in the memory device that are non-functional further contains a record of the size of each non-functional block.

11. A block remapping system for a non-volatile memory device having memory cells arranged in blocks each of which is associated with a respective block address, the system comprising:

a storage device containing a record of the address of each block of memory cells that is non-functional;

a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;

an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

12. The block remapping system of claim 11 wherein the storage device comprises:

an electronic record of non-functional block addresses each of which is associated with a respective index number, the index numbers being assigned to the non-functional block addresses in order from a lowest index number associated with a lowest non-functional block address to a highest index number associated with a highest non-functional block address;

a counter coupled to the electronic record of non-functional block addresses, the counter being operable responsive to being clocked to generate and apply to the electronic record an incrementing sequence of the index numbers.

13. The block remapping system of claim 12 wherein the electronic record comprises sets of fuses that may be selectively programmed to correspond to the non-functional block addresses.

14. The block remapping system of claim 12 wherein the electronic record further contains a record of the size of each block having a non-functional block addresses contained in the electronic record.

15. The block remapping system of claim 11, further comprising:

a second comparator coupled to the storage device, the second comparator being configured to compare each output block address with at least some of the block addresses contained in the storage device, the second comparator being operable to compare each output block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a second adder coupled to receive each output block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the second adder being configured to add to each output block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the output block address.

16. The block remapping system of claim 15 wherein a single comparator is used as the first comparator and the second comparator, and a single adder is used as the first adder and the second adder.

17. A block remapping system for a non-volatile memory device having memory cells arranged in blocks each of which is associated with a respective block address, the system comprising:

a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;

a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;

a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;

a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;

an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;

a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device; and

a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.

18. The block remapping system of claim 17 wherein the storage device comprises sets of fuses that may be selectively programmed to correspond to the block address and block size value for each block of memory cells that is non-functional.

19. The block remapping system of claim 17, further comprising an output address register having a data input coupled to the output of the second multiplexer and having an output on which the output block address is generated responsive to the block address at the output of the second multiplexer being latched into the output address register.

20. The block remapping system of claim 19 wherein the output address register is latched by a signal that increments the counter.

21. A non-volatile memory device, comprising:

a signal bus;

a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;

an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;

a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;

a storage device containing a record of the address of each block of memory cells that is non-functional;

a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;

an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

22. The memory device of claim 21 wherein the storage device comprises:

an electronic record of non-functional block addresses each of which is associated with a respective index number, the index numbers being assigned to the non-functional block addresses in order from a lowest index number associated with a lowest non-functional block address to a highest index number associated with a highest non-functional block address;

a counter coupled to the electronic record of non-functional block addresses, the counter being operable responsive to being clocked to generate and apply to the electronic record an incrementing sequence of the index numbers.

23. The memory device of claim 22 wherein the electronic record comprises sets of fuses that may be selectively programmed to correspond to the non-functional block addresses.

24. The memory device of claim 22 wherein the electronic record further contains a record of the size of each block having a non-functional block addresses contained in the electronic record.

25. The memory device of claim 21, further comprising:

a second comparator coupled to the storage device, the second comparator being configured to compare each output block address with at least some of the block addresses contained in the storage device, the second comparator being operable to compare each output block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a second adder coupled to receive each output block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the second adder being configured to add to each output block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the output block address.

26. The memory device of claim 25 wherein a single comparator is used as the first comparator and the second comparator, and a single adder is used as the first adder and the second adder.

27. The memory device of claim 21 wherein the non-volatile memory cells comprises flash memory cells.

28. A non-volatile memory device, comprising:

a signal bus;

a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;

an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;

a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;

a block remapping system, the system comprising;

a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;

a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;

a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;

a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;

an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;

a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device; and

a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.

29. The memory device of claim 28 wherein the storage device comprises sets of fuses that may be selectively programmed to correspond to the block address and block size value for each block of memory cells that is non-functional.

30. The memory device of claim 28, further comprising an output address register having a data input coupled to the output of the second multiplexer and having an output on which the output block address is generated responsive to the block address at the output of the second multiplexer being latched into the output address register.

31. The memory device of claim 30 wherein the output address register is latched by a signal that increments the counter.

32. The memory device of claim 28 wherein the non-volatile memory cells comprises flash memory cells.

33. A processor-based system, comprising:

a processor operable to process data and to provide memory commands and addresses;

an input device coupled to the processor;

an output device coupled to the processor; and

a non-volatile memory device, comprising;

a signal bus;

a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;

an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;

a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;

a storage device containing a record of the address of each block of memory cells that is non-functional;

a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;

an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

34. The processor-based system of claim 33 wherein the storage device comprises:

an electronic record of non-functional block addresses each of which is associated with a respective index number, the index numbers being assigned to the non-functional block addresses in order from a lowest index number associated with a lowest non-functional block address to a highest index number associated with a highest non-functional block address;

a counter coupled to the electronic record of non-functional block addresses, the counter being operable responsive to being clocked to generate and apply to the electronic record an incrementing sequence of the index numbers.

35. The processor-based system of claim 34 wherein the electronic record comprises sets of fuses that may be selectively programmed to correspond to the non-functional block addresses.

36. The processor-based system of claim 34 wherein the electronic record further contains a record of the size of each block having a non-functional block addresses contained in the electronic record.

37. The processor-based system of claim 33, further comprising:

a second comparator coupled to the storage device, the second comparator being configured to compare each output block address with at least some of the block addresses contained in the storage device, the second comparator being operable to compare each output block address with the block addresses contained in the storage device in order from a lowest address to a highest address;

a second adder coupled to receive each output block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the second adder being configured to add to each output block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the output block address.

38. The processor-based system of claim 37 wherein a single comparator is used as the first comparator and the second comparator, and a single adder is used as the first adder and the second adder.

39. The processor-based system of claim 33 wherein the non-volatile memory cells comprises flash memory cells.

40. A processor-based system, comprising:

a processor operable to process data and to provide memory commands and addresses;

an input device coupled to the processor;

an output device coupled to the processor; and

a non-volatile memory device, comprising;

a signal bus;

a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;

an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;

a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;

a block remapping system, the system comprising;

a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;

a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;

a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;

a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;

an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;

a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device; and

a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.

41. The processor-based system of claim 40 wherein the storage device comprises sets of fuses that may be selectively programmed to correspond to the block address and block size value for each block of memory cells that is non-functional.

42. The processor-based system of claim 40, further comprising an output address register having a data input coupled to the output of the second multiplexer and having an output on which the output block address is generated responsive to the block address at the output of the second multiplexer being latched into the output address register.

43. The processor-based system of claim 42 wherein the output address register is latched by a signal that increments the counter.

44. The processor-based system of claim 40 wherein the non-volatile memory cells comprises flash memory cells.