VERIFICATION SYSTEM AND METHOD FOR BODY CONTROL MODULE SOFTWARE

• US 20080178045A1
• Filed: 10/25/2007
• Published: 07/24/2008
• Est. Priority Date: 10/31/2006
• Status: Abandoned Application

• Current Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Original Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Inventors: Son, Jung Duck
• Application Number:
  US11/924,184
• Publication Number:
  US 20080178045A1
• Time in Patent Office: Days
• US Class Current: 714/38
• CPC Class Codes: G06F 11/3672 Test management

Abstract

The present invention relates to a verification system and method for BCM software wherein data extracted from an orthogonal array are applied to verification for BCM software to reduce the number of tests such that verification for each BCM can be performed in a short period of time before manufacturing a prototype, reliability of verification results can be improved using a verification program regardless of an evaluator, and errors in the software for each BCM can be found and corrected at an early stage.

To this end, the present invention provided a verification system for BCM software which comprises a BCM for controlling functions of convenience equipment in a vehicle; a computer equipped with a verification program and capable of exchanging information with the BCM through serial communication; and a power supply unit for applying power to the computer and the BCM.

Claims

1. A verification system for body control module (BCM) software, comprising:

a BCM for controlling functions of convenience equipment in a vehicle;

a computer equipped with a verification program and capable of exchanging information with the BCM through serial communication; and

a power supply unit for applying power to the computer and the BCM.

2. The verification system as claimed in claim 1, wherein the verification program includes:

an input unit for creating a plurality of input signals into an Excel file using an orthogonal array and then receiving data from the Excel file;

a control unit for allocating the Excel data for respective test conditions to an input port of the BCM, converting the Excel file into a header file which can be compiled by a microcomputer of the BCM and compiling the header file together with the software of the BCM, applying power to the BCM using an on/off control of the power supply unit, allowing input conditions to be inputted to the BCM by means of the inserted header file, receiving the output signal from the BCM, and comparing an output result with a predetermined result to determine whether the BCM is acceptable or not; and

an output unit for receiving the output signal generated in the BCM from the control unit and then storing the received output signal.

3. The verification system as claimed in the claim 2, wherein the plurality of input signals are inputted in a first axis of the orthogonal array, and a plurality of test numbers are inputted in a second of the orthogonal array.

4. The verification system as claimed in the claim 3, wherein the orthogonal array includes an inner orthogonal array in which a plurality of input signals are inputted in a first axis and a plurality of testing numbers are inputted in a second axis, and an outer orthogonal array in which a plurality of testing numbers are inputted in a first axis and a plurality of input signals are inputted in a second axis.

5. The verification system as claimed in the claim 2, wherein the input unit can perform addition and change of a variety of input signals.

6. The verification system as claimed in the claim 2, wherein the output unit performs setting of an output terminal and change of the number of output signals, and automatically performs test process and result determination.

7. A verification method for BCM software, comprising the steps of:

creating a plurality of input signals into an Excel file using an orthogonal array;

inputting orthogonal array data of the Excel file created in the above creating step into an input unit of a verification program;

allocating Excel file data to an input port of the BCM;

converting the Excel file into a header file that can be compiled by a microcomputer of the BCM and compiling the header file together with software of the BCM;

applying power to the BCM using an on/off control of a power supply unit and allowing input conditions to be inputted to the BCM by means of the inserted header file;

allowing a relevant output signal to be generated by the BCM and storing the relevant output signal in an output unit;

allowing the output unit to automatically output a test result and comparing the output result with a predetermined result to determine whether the BCM is acceptable or not;

extracting a cause factor of problem occurrence through an analysis scheme; and

finding an error of the software of the BCM using the cause factor of the problem occurrence.

8. The verification method as claimed in the claim 7, wherein the analysis scheme includes the steps of:

classifying all tests by an inner array criterion of the an inner orthogonal array in which a plurality of input signals are inputted in a first axis and a plurality of testing numbers are inputted in a second axis;

calculating probability of problem occurrence between two input signals for the inner array criterion to create an analysis table;

extracting an input signal commonly included in an input combination with a probability of problem occurrence of 1 as a cause factor of problem occurrence; and

finding an error of the software by reviewing a routine of the software for controlling the input signal extracted as the cause factor of problem occurrence.

9. The verification method as claimed in the claim 8, wherein the probability of problem occurrence between the two input signals is expressed as (a test result)/(the number of tests), where the test result is the number of input combinations simultaneously satisfying a level of one input signal of the two input signals and a level of the other input signal of the two input signals, which are determined to be no good (NG), and the number of tests is the total number of tests which simultaneously satisfy the levels of the two input signals.