HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD
First Claim
1. A built-in self test (BIST) architecture comprising:
- a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; and
command multipliers in communication with said controller and associated with said memory arrays,wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, andwherein each specific command multiplier is adapted to selectively operate in one of two modes;
a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, anda second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency.
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Accused Products
Abstract
Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
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Citations
35 Claims
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1. A built-in self test (BIST) architecture comprising:
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a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; and command multipliers in communication with said controller and associated with said memory arrays, wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, and wherein each specific command multiplier is adapted to selectively operate in one of two modes; a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A built-in self test (BIST) architecture comprising:
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a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; and command multipliers in communication with said controller and associated with said memory arrays, wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, wherein said controller further comprises a first address generator adapted to generate initial addresses for said instructions, wherein said command multipliers each further comprise a second address generator adapted to generate final addresses for said instructions, and wherein each specific command multiplier is adapted to selectively operate in one of two modes; a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A built-in self test (BIST) architecture comprising:
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a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; command multipliers in communication with said controller and associated with said memory arrays, wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, and wherein each specific command multiplier is adapted to selectively operate in one of two modes; a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency; and synchronization circuits adapted to provide synchronization between said command multipliers and said controller. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A built-in self test (BIST) method comprising:
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receiving, from a controller, instructions for performing test functions on a memory array, wherein said controller has a lower operating frequency relative to a higher operating frequency of said memory array; and selectively performing said test functions at one of said higher operating frequency and said lower operating frequency. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A built-in self test (BIST) method comprising:
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communicating, by a controller to a plurality of command multipliers, instructions for performing test functions on a plurality of memory arrays, wherein said controller operates at a lower operating frequency than said memory arrays and wherein said instructions specify one of a first mode and a second mode; synchronizing, by a plurality of synchronization circuits, timing between said controller and each of said command multipliers; and selectively operating, by said command multipliers, in one of said first mode and said second mode, wherein, for each specific command multiplier, said operating in said first mode comprises multiplying said instructions so that said test functions are performed on a specific memory array at a higher operating frequency of said specific memory array, and wherein, for said each specific command multiplier, said operating in said second mode comprises suspending multiplication of said instructions so that said test functions are performed on said specific memory array at said lower operating frequency. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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Specification