HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD

• US 20080178053A1
• Filed: 03/28/2008
• Published: 07/24/2008
• Est. Priority Date: 01/29/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gorman, Kevin W., Paparelli, Adrian J., Roberge, Michael A.
• Granted Patent: US 7,631,236 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.

Claims

1. A built-in self test (BIST) architecture comprising:

a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; and

command multipliers in communication with said controller and associated with said memory arrays,

wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, and

wherein each specific command multiplier is adapted to selectively operate in one of two modes;

a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and

a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency.

2. The BIST architecture of claim 1, wherein said instructions specify one of said first mode and said second mode,

wherein said higher operating frequency is n times said lower operating frequency,

where n may differ between said memory arrays, and

wherein said command multipliers are adapted to multiply each of said instructions by n when said instructions specify said first mode.

3. The BIST architecture of claim 1, wherein said first mode allows said test functions to be performed at said higher operating frequency with limitations on test pattern flexibility and wherein said second mode allows said test functions to be performed at said lower operating frequency without said limitations on test pattern flexibility.

4. The BIST architecture of claim 1, wherein said controller further comprises a first address generator adapted to generate initial addresses for said instructions and wherein said command multipliers each further comprise a second address generator adapted to generate final addresses.

5. The BIST architecture of claim 1, wherein said controller is adapted to communicate the same set of instructions to all said command multipliers,

wherein said command multipliers are each adapted to translate said same set of instructions into commands for performing said test functions locally, and

wherein, for each of said command multipliers, said commands are specific to said specific memory array.

6. The BIST architecture of claim 1, wherein said command multipliers are each further adapted to support programmable command sequences.

7. The BIST architecture of claim 1, wherein said command multipliers are each further adapted to provide data scrambling specific to said corresponding memory array.

8. A built-in self test (BIST) architecture comprising:

a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays; and

command multipliers in communication with said controller and associated with said memory arrays,

wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays,

wherein said controller further comprises a first address generator adapted to generate initial addresses for said instructions,

wherein said command multipliers each further comprise a second address generator adapted to generate final addresses for said instructions, and

wherein each specific command multiplier is adapted to selectively operate in one of two modes;

a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and

a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency.

9. The BIST architecture of claim 8, wherein said instructions specify one of said first mode and said second mode,

wherein said higher operating frequency is n times said lower operating frequency,

where n may differ between said memory arrays, and

wherein said command multipliers are adapted to multiply each of said instructions by n when said instructions specify said first mode.

10. The BIST architecture of claim 8, wherein said first mode allows said test functions to be performed at said higher operating frequency with limitations on test pattern flexibility and wherein said second mode allows said test functions to be performed at said lower operating frequency without said limitations on test pattern flexibility.

11. The BIST architecture of claim 8, wherein said controller is adapted to communicate the same set of instructions to all said command multipliers,

wherein said command multipliers are each adapted to translate said same set of instructions into commands for performing said test functions locally, and

wherein, for each of said command multipliers, said commands are specific to said specific memory array.

12. The BIST architecture of claim 8, wherein said command multipliers are each further adapted to support programmable command sequences.

13. The BIST architecture of claim 8, wherein said command multipliers are each further adapted to provide data scrambling specific to said corresponding memory array.

14. A built-in self test (BIST) architecture comprising:

a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays;

command multipliers in communication with said controller and associated with said memory arrays,

wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, and

wherein each specific command multiplier is adapted to selectively operate in one of two modes;

a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and

a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency; and

synchronization circuits adapted to provide synchronization between said command multipliers and said controller.

15. The BIST architecture of claim 14, wherein said synchronization circuits comprise one of separate circuits between said command multipliers and said controller and embedded circuits within said command multipliers.

16. The BIST architecture of claim 14, wherein said instructions specify one of said first mode and said second mode,

wherein said higher operating frequency is n times said lower operating frequency,

wherein n may differ between said memory arrays, and

wherein said command multipliers are adapted to multiply each of said instructions by n when said code specifies said first mode.

17. The BIST architecture of claim 14, wherein said first mode allows said test functions to be performed at said higher operating frequency with limitations on flexibility and wherein said second mode allows said test functions to be performed at said lower operating frequency without said limitations on flexibility.

18. The BIST architecture of claim 14, wherein said controller further comprises a first address generator adapted to generate initial addresses for said instructions and wherein said command multipliers each further comprise a second address generator adapted to generate final addresses.

19. The BIST architecture of claim 14, wherein said controller is adapted to communicate the same set of instructions to all said command multipliers,

wherein said command multipliers are adapted to translate said same set of instructions into commands for performing said test functions locally, and

wherein, for each said specific command multiplier, said commands are specific to said specific memory array.

20. The BIST architecture of claim 14, wherein said command multipliers are each further adapted to support programmable command sequences.

21. The BIST architecture of claim 14, wherein said command multipliers are each further adapted to provide data scrambling specific to said memory array.

22. A built-in self test (BIST) method comprising:

receiving, from a controller, instructions for performing test functions on a memory array, wherein said controller has a lower operating frequency relative to a higher operating frequency of said memory array; and

selectively performing said test functions at one of said higher operating frequency and said lower operating frequency.

23. The method of claim 22, wherein said higher operating frequency is n times said lower operating frequency, and

wherein said performing of said test functions at said higher operating frequency comprises multiplying each of said instructions by n when said instructions.

24. The method of claim 22, wherein said method further comprises translating said instructions into commands for performing said test functions such that said commands are memory array-specific.

25. The method of claim 22, wherein said performing of said test functions at said higher operating frequency limits test pattern flexibility and wherein said performing of said test functions at said lower operating frequency does not limit said test pattern flexibility.

26. The method of claim 22, further comprising using a hierarchical addressing scheme.

27. The method of claim 22, further comprising locally supporting programmable command sequences.

28. The method of claim 22, further comprising locally providing data scrambling such that said data scrambling is memory array-specific.

29. A built-in self test (BIST) method comprising:

communicating, by a controller to a plurality of command multipliers, instructions for performing test functions on a plurality of memory arrays, wherein said controller operates at a lower operating frequency than said memory arrays and wherein said instructions specify one of a first mode and a second mode;

synchronizing, by a plurality of synchronization circuits, timing between said controller and each of said command multipliers; and

selectively operating, by said command multipliers, in one of said first mode and said second mode,

wherein, for each specific command multiplier, said operating in said first mode comprises multiplying said instructions so that said test functions are performed on a specific memory array at a higher operating frequency of said specific memory array, and

wherein, for said each specific command multiplier, said operating in said second mode comprises suspending multiplication of said instructions so that said test functions are performed on said specific memory array at said lower operating frequency.

30. The method of claim 29, wherein said higher operating frequency is n times said lower operating frequency,

wherein n may differ between said memory arrays, and

wherein said multiplying comprises multiplying each of said instructions by n when said instructions specify said first mode.

31. The method of claim 29, wherein said communicating comprises communicating a same set of instructions to all of said command multipliers and wherein said method further comprises, for each of said memory arrays, uniquely translating said same set of command instructions into commands for performing said test functions locally such that said commands are memory array-specific.

32. The method of claim 29, wherein said performing of said test functions in said first mode allows said test functions to be performed at said higher operating frequency with limitations on test pattern flexibility and wherein said performing of said test functions in said second mode allows said test functions to be performed at said lower operating frequency without said limitations on test pattern flexibility.

33. The method of claim 29, further comprising using a hierarchical addressing scheme.

34. The method of claim 29, further comprising, for each of said memory arrays, locally supporting programmable command sequences.

35. The method of claim 29, further comprising, for each of said memory arrays, locally providing data scrambling such that said data scrambling is memory array-specific.