Test pattern generation circuit having plural pseudo random number generation circuits supplied with clock signals at different timing respectively

• US 20080178055A1
• Filed: 01/23/2008
• Published: 07/24/2008
• Est. Priority Date: 01/24/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Nakamura, Hisashi
• Application Number:
  US12/010,264
• Publication Number:
  US 20080178055A1
• Time in Patent Office: Days
• US Class Current: 714/735
• CPC Class Codes: G01R 31/31813 Test pattern generators

Abstract

A test pattern generation circuit has multiple pseudo random number generation circuits and a clock control circuit. The pseudo random number generation circuits are provided corresponding to the respective signal lines in a bus wiring, and have predetermined first initial values, which take the same value. In response to first clock signals, the pseudo random number generation circuits generate pseudo random numbers including the first initial values as starting values. According to the value of a control signal, the clock control circuit determines the output-start timings of the first clock signals to be respectively provided to the multiple pseudo random number generation circuits.

Claims

1. A test pattern generation circuit, comprising:

a plurality of pseudo random number generation circuits which are provided respectively corresponding to signal lines in a bus wiring, which each have a first initial value set to be the same value in advance, and which generates pseudo random numbers having the first initial value as a starting value in response to a first clock signal; and

a clock control circuit that determines, according to a value of a control signal, each of output-start timings of the first clock signals respectively provided to the plurality of pseudo random number generation circuits.

2. The test pattern generation circuit according to claim 1, wherein the pseudo random number generation circuits each comprise a shift register with feedback via an exclusive OR circuit.

3. The test pattern generation circuit according to claim 2,

wherein the clock control circuit includes a first clock control circuit, which receives reference clocks as an input signal, and sets, according to the value of the control signal, a shift amount in timings of starting supply of the first clock signals to the plurality of pseudo random number generation circuits.

4. The test pattern generation circuit according to claim 2,

wherein the clock control circuit includes a first clock control circuit which receives reference clocks as an input signal, which determines whether to output the reference clock signal by using a shift amount in timings of starting supply of the first clock signals to the plurality of pseudo random number generation circuits, according to the control signal, the shift amount being set in advance.

5. The test pattern generation circuit according to claim 3,

wherein the clock control circuit includes a second clock control circuit which receives the first clock signal as an input signal, and sets, according to the value of the control signal, a shift amount in timings of starting supply of the first clock signals to the plurality of pseudo random number generation circuits.

6. The test pattern generation circuit according to claim 3,

wherein the clock control circuit includes a second clock control circuit which receives the first clock as an input signal, which determines whether to output the reference clock signal by using a shift amount in timings of starting supply of the first clock signals to the plurality of pseudo random number generation circuits, according to the control signal, the shift amount being set in advance.

7. The test pattern generation circuit according to claim 5, wherein the clock control circuit is connected to circuits to be tested, each of said circuits to be tested respectively corresponding to the first clock control circuit and the second clock control circuit.

8. The test pattern generation circuit according to claim 3, wherein:

the first clock control circuit includes a first counter and a clock gating circuit;

the first counter counts a number of clocks of the reference clocks, and outputs a stop signal when the counted value reaches a predetermined value; and

the clock gating circuit receives the reference clocks and outputs the reference clocks as the first clock signal, until receiving the stop signal.

9. The test pattern generation circuit according to claim 5, wherein the second clock control circuit receives, as an input, the first clock signals outputted by the first clock control circuit.

10. The test pattern generation circuit according to claim 2, wherein,

the control signal includes at least one of a first control signal and a second control signal,

under control based on the first control signal, the clock control circuit sets, according to a value of the first control signal, a shift amount in timings of starting supply of the first clock signals to the plurality of pseudo random number generation circuits,

under control based on the second control signal, the clock control circuit determines whether to output the reference clock signal by using a shift amount in supply starting timings set in advance.

11. The test pattern generation circuit according to claim 1, further comprising a selector which selects one of the first clock signal and a second clock signal, and provides the selected clock signal to each of the plurality of pseudo random number generation circuits.

12. The test pattern generation circuit according to claim 1,

wherein the plurality of pseudo random number generation circuits each have a second initial value set to a certain value based on the first initial value and the first clock signal, and each output, as the test patterns, pseudo random numbers having the second initial value as a starting value.

13. A test circuit, comprising:

the test pattern generation circuit according to claim 1;

a comparator that compares pseudo random numbers inputted from an interface circuit, with pseudo random numbers outputted by the plurality of pseudo random number generation circuits in the test pattern generation circuit; and

a result holding circuit that holds test results outputted by the comparator and outputting the test results.

14. A test pattern generation circuit, comprising:

a clock control circuit which outputs a plurality of clock signals, each of said clock signals being outputted at a timing based on a control signal; and

a plurality of pseudo random number generation circuits, which each have the same initial value, and which each generates pseudo random numbers having the initial value as a starting value in response to a corresponding one of said clock signals.

15. The test pattern generation circuit as claimed in claim 14, wherein said clock control circuit comprises:

a first counter which counts a reference clock;

a first comparator which compares an output of said first counter with a value of said control signal and outputs a first enable signal when the output of said first counter and said value of said control signal are matched; and

a first clock gating circuit which outputs said reference signal as a first one of said clock signals when said first enable signal is inputted.

16. The test pattern generation circuit as claimed in claim 15, wherein said clock control circuit further comprises:

a second counter which counts said first one of said clock signals;

a second comparator which compares an output of said second counter with a value of said control signal and outputs a second enable signal when the output of said second counter and said value of said control signal are matched; and

a second clock gating circuit which outputs said first one of said clock signals as a second one of said clock signals when said second enable signal is inputted.

17. The test pattern generation circuit as claimed in claim 16, further comprising:

a selector which selectively outputs one of said clock signals or a test clock.

18. The test pattern generation circuit as claimed in claim 14, wherein said clock control circuit comprises:

a first counter which counts a reference clock and outputs a stop signal when a counted number reaches a predetermined number;

a first clock gating circuit which outputs said reference signal as one of said clock signals and stops outputting said reference signal when said stop signal is inputted;

a second counter which counts said one of said clock signals;

a comparator which compares an output of said second counter with a value of said control signal and outputs an enable signal when the output of said second counter and said value of said control signal are matched; and

a clock gating circuit which outputs said one of said clock signals as a second one of said clock signals when said enable signal is inputted.

19. The test pattern generation circuit as claimed in claim 14, further comprising:

a second clock control circuit which receives the clock signals and outputs a plurality of second clock signals, each of said second clock signals being outputted at a timing based on a second control signal; and

a plurality of second pseudo random number generation circuits, which each has the same initial value, and which each generates pseudo random numbers having the initial value as a starting value in response to a corresponding one of said second clock signals.

20. The test pattern generation circuit as claimed in claim 19, wherein, said second clock control circuit comprises a plurality of clock gating circuits which receive the respective one of clock signals.