Apparatus and methods for electrochemical processing of microfeature wafers

• US 20080179180A1
• Filed: 01/29/2007
• Published: 07/31/2008
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Inventors: Woodruff, Daniel J., McHugh, Paul R., Wilson, Gregory J.
• Granted Patent: US 7,842,173 B2
• Time in Patent Office: Days
• US Class Current: 204/164
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 17/10 Electrodes , e.g. composition, counter electrode
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: C25F 3/30 of semiconducting materials

Abstract

Apparatus and methods for electrochemically processing microfeature wafers. The apparatus can have a vessel including a processing zone in which a microfeature wafer is positioned for electrochemical processing. The apparatus further includes at least one counter electrode in the vessel that can operate as an anode or a cathode depending upon the particular plating or electropolishing application. The apparatus further includes a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending upon the type of process. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode in the vessel when the wafer is in the processing zone

Claims

1. An apparatus for electrochemically processing a microfeature wafer, comprising:

a vessel having a processing zone in which a microfeature wafer is positioned for electrochemical processing;

at least one counter electrode in the vessel;

a supplementary electrode configured to operate independently from the counter electrode; and

a supplementary virtual electrode in the processing zone, wherein the supplementary virtual electrode is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode when the wafer is in the processing zone.

2. The apparatus of claim 1 wherein the supplementary electrode is located above the counter electrode.

3. The apparatus of claim 1 wherein the supplementary electrode is located above the processing zone.

4. The apparatus of claim 1 wherein the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter, and wherein the supplementary electrode is located above the member at a radial position between the inner edge and the perimeter.

5. The apparatus of claim 4 wherein the supplementary virtual electrode has an aperture for shaping an electric field component from the supplementary electrode, and wherein the aperture is formed, at least in part, by the inner edge of the member.

6. The apparatus of claim 1 wherein:

the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter;

the apparatus further includes a mount above the member, wherein the mount and the member form a compartment having a first flow outlet between the mount and the member through which a portion of the processing fluid can exit the processing zone and flow over the perimeter of the member, and wherein the mount includes a brim defining a second flow outlet for the processing fluid; and

the supplementary electrode is in the compartment at a radial position between the inner edge and the perimeter.

7. The apparatus of claim 6 wherein the supplementary virtual electrode has an aperture for shaping an electric field component from the supplementary electrode, and wherein the aperture is formed, at least in part, by the inner edge of the member.

8. The apparatus of claim 1, further comprising a plurality of counter electrodes, and wherein the counter electrodes are configured to be operated independently from each other and the supplementary electrode.

9. The apparatus of claim 8, further comprising a plurality of virtual counter electrodes corresponding to the counter electrodes, wherein the virtual counter electrodes have apertures located below the virtual supplementary electrode.

10. The apparatus of claim 1, further comprising a wafer holder having a wafer support configured to hold a microfeature wafer and an electrical contact, and wherein the virtual supplementary electrode has an aperture defined, at least in part, by the vessel and the wafer holder.

11. The apparatus of claim 1 wherein:

the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter; and

the apparatus further comprises a wafer holder having a wafer support configured to hold a microfeature wafer and an electrical contact configured to contact a plating surface of the wafer, and wherein the virtual supplementary electrode has an aperture defined, at least in part, by the inner edge of the member and the wafer support of the wafer holder.

12. The apparatus of claim 11 wherein the aperture of the supplementary virtual electrode has an outer diameter defined by the inner edge of the member and an inner diameter defined by an outer diameter of a portion of the wafer support.

13. The apparatus of claim 12 wherein the aperture of the supplementary virtual electrode has a first width at one side of the wafer holder and a second width different than the first width at an opposing side of the wafer holder.

14. The apparatus of claim 1 wherein the virtual supplementary electrode has an aperture with a first width at one side of the processing zone and a second width different than the first width at an opposing side of the processing zone when a central axis of the wafer is offset relative to a central axis of an electric field of the counter electrode.

15. An apparatus for electrochemically processing a microfeature wafer, comprising:

a vessel having a processing zone through which a processing fluid can flow upward, a rim over which the processing fluid can flow out of the processing zone, and a perimeter radially outward from the rim over which the processing fluid can flow downwardly;

a wafer holder having a support configured to hold a microfeature wafer in the processing zone and at least one electrical contact configured to provide an electrical current to the wafer;

at least one counter electrode in the vessel;

a supplementary electrode spaced apart from the wafer holder; and

a virtual supplementary electrode having an aperture configured to shape an electric field component from the supplementary electrode, wherein the aperture is shaped, at least in part, by alignment between the wafer holder and the vessel to counteract non-uniformities associated with an offset between the wafer holder and the vessel when the wafer holder holds a wafer in the processing zone.

16. The apparatus of claim 15 wherein the aperture of the supplementary virtual electrode has an outer diameter defined by a portion of the vessel and an inner diameter defined by an outer diameter of a portion of the support of the wafer holder.

17. The apparatus of claim 16 wherein the aperture of the supplementary virtual electrode has a first width at one side of the wafer holder and a second width different than the first width at an opposing side of the wafer holder.

18. The apparatus of claim 15 wherein the virtual supplementary electrode has an aperture with a first width at one side of the processing zone and a second width different than the first width at an opposing side of the processing zone when a central axis of the wafer is offset relative to a central axis of an electric field of the counter electrode.

19. An apparatus for electrochemically processing a microfeature wafer, comprising:

a vessel configured to direct a flow of processing fluid upward, wherein the vessel includes a processing zone through which the upward flow of processing fluid can pass;

a wafer holder having a wafer support configured to hold a microfeature wafer at the processing zone in a position transverse to the upward flow of processing fluid and at least one electrical contact configured to contact a plating surface of the wafer;

at least one counter electrode in the vessel;

a stationary supplementary electrode; and

a supplementary virtual electrode associated with the supplementary electrode, wherein the supplementary virtual electrode has an aperture with an outer edge define at least in part by the vessel and an inner edge defined at least in part by the wafer holder when the wafer holder holds a wafer in the processing zone.

20. The apparatus of claim 19, further comprising a plurality of counter electrodes, and wherein the counter electrodes are configured to be operated independently from each other and the supplementary electrode.

21. The apparatus of claim 20, further comprising a plurality of virtual counter electrodes corresponding to the counter electrodes, wherein the virtual counter electrodes have apertures located below the virtual supplementary electrode.

22. The apparatus of claim 21 wherein an outermost virtual counter electrode has an outer diameter greater than an outer diameter of the wafer.

23. The apparatus of claim 19, further comprising an agitator between the virtual counter electrodes and the wafer holder.

24. A method for electrochemically processing a microfeature wafer, comprising:

positioning a wafer holder such that a microfeature wafer in the wafer holder is at a processing zone of the vessel;

establishing an electric field in a processing fluid in the vessel using the wafer, a counter electrode in the vessel, and a supplementary electrode that is spaced apart from the wafer holder; and

counteracting an offset of the electric field relative to the wafer associated with an offset between the wafer holder and the vessel when the wafer holder holds a wafer in the processing zone.

25. The method of claim 24 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode in the processing zone, and wherein counteracting for the offset of the electric field relative to the wafer comprises shaping the supplementary virtual electrode to have a first width at a first side of the wafer holder and a second width different than the first width at a second side of the wafer holder.

27. The method of claim 24, further comprising flowing the processing fluid upwardly through the processing zone and over a rim.

28. The method of claim 27 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode in the processing zone, and wherein counteracting for the offset of the electric field relative to the wafer comprises shaping the supplementary virtual electrode to have a first width at a first side of the wafer holder and a second width different than the first width at a second side of the wafer holder.

31. The method of claim 24 wherein the supplementary electrode is located above the processing zone, and the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

32. The method of claim 24 wherein the supplementary electrode is located above the counter electrode, and the method further comprises de-plating material using the supplementary electrode.

33. The method of claim 24 wherein the supplementary electrode is located above the processing zone, and the method further comprises de-plating material using the supplementary electrode.

34. The method of claim 24 wherein the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter, and wherein the supplementary electrode is located above the member at a radial position between the inner edge and the perimeter, and wherein the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

35. The method of claim 34 wherein the supplementary virtual electrode has an aperture for shaping an electric field component from the supplementary electrode, and wherein the aperture is formed, at least in part, by the inner edge of the member, and wherein the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

36. The method of claim 24 wherein:

the vessel includes a member having an inner edge defining, a rim above the inner edge, and a perimeter;

the apparatus further includes a mount above the member, wherein the mount and the member form a compartment having a first flow outlet between the mount and the member through which a portion of the processing fluid can exit the processing zone and flow over the perimeter of the member, and wherein the mount includes a brim defining a second flow outlet for the processing fluid;

the supplementary electrode is in the compartment at a radial position between the inner edge and the perimeter; and

the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

37. The method of claim 36 wherein the supplementary virtual electrode has an aperture for shaping an electric field component from the supplementary electrode, and wherein the aperture is formed, at least in part, by the inner edge of the member, and wherein the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

38. The method of claim 24, wherein the method further comprises establishing the electric field using a plurality of counter electrodes and operating the counter electrodes independently from each other and the supplementary electrode.

39. The method of claim 24 wherein counteracting the offset comprises configuring at least one of an inner edge of the vessel and an outer surface of the wafer holder to have a shape that defines a supplementary virtual electrode that compensates for the offset.

40. The method of claim 39, further comprising changing a shape of at least one of the inner edge of the vessel or the outer surface of the wafer holder.

41. The method of claim 39, further comprising replacing the inner edge or the wafer holder with a different inner edge or wafer holder.

26. The method of 24 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode defined, at least in part, by a portion of the vessel at the processing zone and a portion of the wafer holder.

29. The method of 27 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode defined, at least in part, by a portion of the vessel at the processing zone and a portion of the wafer holder.

30. The method of 24 wherein the '"'"'supplementary electrode is located above the counter electrode, and the method further comprises plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.