Wafer level phosphor coating method and devices fabricated utilizing method

• US 20080179611A1
• Filed: 09/07/2007
• Published: 07/31/2008
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Seruto, James, Britt, Jeffrey C., Ibbetson, James, Keller, Bernd, Bergmann, Michael J., Chakraborty, Arpan, Tarsa, Eric, Emerson, David T., Edmond, John, Fu, Yankun, Chitnis, Ashay, Cabalu, Jasper S.
• Granted Patent: US 9,159,888 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0091 Scattering means in or on the semiconductor body or semiconductor body package H01L33/22 takes precedence
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/508 having a non-uniform spatial arrangement or non-uniform concentration, e.g. patterned wavelength conversion layer, wavelength conversion layer with a concentration gradient of the wavelength conversion material
• CPC Class Codes: H01L 33/54 having a particular shape
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.

Claims

1. An light emitting diode (LED) chip, comprising:

an LED having a textured surface;

a contact on said LED;

a pedestal in electrical contact with said contact; and

a coating at least partially covering said LED, said pedestal extending through said coating and exposed for electrical contact.

2. The LED chip of claim 1, wherein said pedestal extends to the surface of said coating and is exposed at the surface of said coating.

3. The LED chip of claim 1, wherein said LED emits white light.

4. The LED chip of claim 1, wherein said coating is on the top surface of said LED.

5. The LED chip of claim 1, wherein said coating is on the top and side surfaces of said LED.

6. The LED chip of claim 1, wherein said LED is on a substrate.

7. The LED chip of claim 6, wherein said coating is also on the side surfaces of said substrate.

8. The LED chip of claim 1, further comprising a current spreading structure.

9. The LED chip of claim 1, further comprising a current spreading layer.

10. The LED chip of claim 1, wherein the surface of said coating is textured.

11. The LED chip of claim 1, wherein said coating is shaped.

12. The LED chip of claim 1, wherein said coating comprises one or more phosphors.

13. The LED chip of claim 8, wherein said coating comprises portions having different concentrations of phosphors.

14. The LED chip of claim 1, wherein said pedestal comprises one or more stud bumps.

15. The LED chip of claim 1, wherein said pedestal comprises a microwire.

16. The LED chip wafer of claim 1, further comprising a reflective layer formed integral to said substrate.

17. A light emitting diode (LED) package comprising:

an LED chip mounted to a submount;

a lens mounted over said LED, such that light from said LED chip emits from said package through said lens, wherein each LED chip comprises;

an LED;

an integral coating at least partially covering said LED, and not covering said submount.

18. The LED package of claim 17, wherein said integral coating is formed by at least partially covering said LED with said at the wafer level and curing said coating at the wafer level.

19. The LED package of claim 17, further comprising a reflective cup mounted to a submount, said LED mounted within said reflective cup with said coating not covering said reflective cup.

20. The LED package of claim 17, further comprising a pedestal in electrical contact with said LED, said pedestal extending through said coating and exposed for electrical contact.

21. The LED package of claim 20, wherein said pedestal extends to the surface of said coating and is exposed at the surface of said coating.

22. The LED package of claim 17, wherein a surface of said LED is textured;

23. The LED package of claim 17, wherein the surface of said coating is textured.

24. The LED package of claim 17, further comprising a current spreading structure on said LED.

25. The LED package of claim 17, wherein said lens is flat.

26. The LED package of claim 17, further comprising and encapsulant between said LED and said lens, said lens in contact with the encapsulant.

27. The LED package of claim 17, wherein said lens is in contact with said LED.

28. The LED package of claim 17, emitting a white light.

29. An light emitting diode (LED) chip, comprising:

an LED mounted on substrate;

a integral coating at least partially covering said LED, said integral coating formed by at least partially covering said LED with said coating at the wafer level and curing said coating at the wafer level.

30. The LED chip of claim 29, wherein said coating is on the top surface of said LED.

31. The LED chip of claim 29, wherein said coating is on the top and side surfaces of the LED.

32. The LED chip of claim 29, wherein said coating is on the top and side surfaces of said LED and on the side surfaces of said substrate.

33. The LED chip of claim 29, wherein said coating is on the bottom surface of said substrate.

34. The LED chip of claim 29, further comprising a reflective layer.

35. The LED chip of claim 29, wherein the surface of said LED is textured.

36. The LED chip of claim 29, wherein said substrate is at least partially transparent.

37. The LED chip of claim 29, wherein said substrate is opaque.

38. The LED chip of claim 29, further comprising a pedestal in electrical contact with said LED and extending through and to the surface of said coating and exposed at the surface of said coating.

39. The LED chip of claim 29, further comprising a current spreading structure.

40. The LED chip of claim 29, further comprising a current spreading layer.

41. The LED chip of claim 29, wherein the surface of said coating is textured.

42. The LED chip of claim 29, wherein said coating is shaped.

43. The LED chip of claim 29, wherein said coating comprises one or more phosphors.

44. The LED chip of claim 43, wherein said coating comprises portions having different concentrations of phosphors.

45. A method for fabricating light emitting diode (LED) chips, comprising:

providing a plurality of LEDs on a surface of a substrate;

depositing pedestals, each of said pedestals in electrical contact with one of said LEDs;

forming grooves in said substrate, at least some of said grooves between adjacent LEDs;

forming a coating over said LEDs, said coating burying at least some of said pedestals; and

thinning said coating leaving at least some of said coating on said LEDs while exposing at least some of said buried pedestals.

46. The method of claim 45, further comprising thinning said substrate.

47. The method of claim 46, wherein said substrate is thinned from its surface opposite said grooves.

48. The method of claim 45, further comprising singulating said LEDs.

49. The method of claim 47, wherein said thinning leaves a stabilization portion of said substrate between the bottom of said grooves and the surface of said substrate opposite said grooves, further comprising singulating said LEDs by cutting through said stabilization portion and said coating.

50. The method of claim 49, wherein at least some of said singulated LEDs comprise an LED, pedestal, a portion of said coating, and a portion of said substrate, said coating at least partially covering said LED and part of the side surface of said substrate.

51. The method of claim 46, wherein said coating at least partially fills said grooves and said thinning thins said substrate to the bottom of said grooves, further comprising singulating said LEDs by cutting through the coating between adjacent ones of said LEDs.

52. The method of claim 51, wherein at least some of said singulated LEDs comprise an LED, pedestal, a portion of said coating, and a portion of said substrate, said coating at least partially covering said LED and substantially all of the side surface of said substrate.

53. The method of claim 48, wherein said singulated LEDs comprise a portion of said coating, said portion being shaped or patterned.

54. The method of claim 45, wherein said LED chips emit white light.

55. The method of claim 45, wherein at least some of said pedestals comprise one or more stud bumps.

56. The method of claim 45, wherein at least some of said pedestals comprise a microwire.

57. The method of claim 45, further comprising depositing a contact on each of said LEDs said pedestals formed on said contacts.

58. The method of claim 45, further comprising forming a current spreading structure on said LEDs, each in electrical contact with at least one of said contacts.

59. The method of claim 45, further comprising depositing at least one current spreading layer.

60. The method of claim 45, wherein said LEDs are flip-chip mounted on a carrier substrate.

61. The method of claim 45, wherein said LEDs comprise at least a portion of a growth substrate.

62. The method of claim 45, further comprising forming a surface texture on said coating.

63. The method of claim 62, wherein said surface texture comprises texturing features sized greater that 10% of the thickness of said coating.

64. The method of claim 45, further comprising forming a surface texture on said LED.

65. The method of claim 64, wherein said surface texture comprises texturing features sized greater that 10% of the thickness of said LED.

66. The method of claim 45, wherein said coating comprises a phosphor loaded binder.

67. The method of claim 45, wherein said coating comprises scattering particles.

68. The method of claim 45, wherein said coating comprises multiple layers with different compositions.

69. The method of claim 45, further comprising depositing a metal pad on said planarized coating interconnecting at least some of said pedestals to form an LED array.

70. The method of claim 45, further comprising mounting one of said LEDs to a submount or printed circuit board (PCB).

71. A light emitting diode (LED) chip wafer, comprising:

a plurality of LEDs having at least one textured surface to enhance light extraction;

a plurality of pedestals, each of which is in electrical contact with one of said LEDs; and

a coating at least partially covering said LEDs, at least some of said pedestals extending through and exposed for electrical contact.

72. The LED chip wafer of claim 71, wherein at least some of said pedestals extend to the surface of said coating and are exposed at the surface of said coating.

73. The LED chip wafer of claim 71, wherein at least one of said pedestals comprises stud bumps.

74. The LED chip wafer of claim 71, wherein at least one of said pedestals comprises a microwire.

75. The LED chip wafer of claim 71, further comprising at least one current spreading structure on one of said LEDs, said current spreading structure in electrical contact with at least one of said contacts.

76. The LED chip wafer of claim 71, further comprising at least one current spreading layer.

77. The LED chip wafer of claim 71, wherein said textured LED surface comprises texture features that are larger than 10% of the thickness of said LED.

78. The LED chip wafer of claim 71, said coating comprises a textured surface.

79. The LED chip wafer of claim 78, wherein said coating textured surface has features larger that 10% of the thickness of said coating.

80. The LED chip wafer of claim 71, further comprising a groove between two adjacent LEDs, said coating at least partially filling said groove.

81. The LED chip wafer of claim 71, wherein said coating comprises multiple phosphors.

82. The LED chip wafer of claim 71, wherein said coating comprises scattering particles.

83. The LED chip wafer of claim 71, wherein said coating comprises a phosphor loaded binder.

84. The LED chip wafer of claim 71, wherein said LEDs are interconnected in an LED array.

85. The LED chip wafer of claim 71, further comprising a reflective layer formed integral to said substrate wafer.

86. The LED chip wafer of claim 71, wherein said coating comprises multiple portions with different concentrations of phosphors.

87. The LED chip wafer of claim 71, capable of emitting white light from said LEDs and coating.