ENHANCED STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY USING AN ADDITIONAL STRESS LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE

• US 20080179661A1
• Filed: 10/02/2007
• Published: 07/31/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Richter, Ralf, Gerhardt, Martin, Hohage, Joerg, Mazur, Martin
• Granted Patent: US 7,994,059 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

Claims

1. A method, comprising:

forming a first stress-inducing layer above a plurality of first transistors formed above a substrate, said first stress-inducing layer generating a first type of stress;

forming a second stress-inducing layer above a plurality of second transistors, said second stress-inducing layer generating a second type of stress other than said first type of stress; and

forming a third stress-inducing layer above said first and second transistors, said third stress-inducing layer generating one of said first and second types of stress.

2. The method of claim 1, wherein a thickness of said first stress-inducing layer is different from a thickness of said second stress-inducing layer.

3. The method of claim 1, further comprising removing a portion of said third stress-inducing layer from above one of said first and second transistors.

4. The method of claim 3, further comprising forming a fourth stress-inducing layer generating a different type of stress relative to said third stress-inducing layer.

5. The method of claim 4, further comprising removing a portion of said fourth stress-inducing layer from above said third stress-inducing layer.

6. The method of claim 1, further comprising reducing said stress generated by said third stress-inducing layer selectively above said first stress-inducing layer when said third stress-inducing layer generates said second type of stress, and reducing said stress generated by said third stress-inducing layer selectively above said second stress-inducing layer when said third stress-inducing layer generates said first type of stress.

7. The method of claim 1, wherein a sum of a thickness of said first stress-inducing layer and a thickness of said second stress-inducing layer is equal to or greater than a sum of a thickness of said third stress-inducing layer and the thickness of said first stress-inducing layer and a sum of the thickness of said third stress-inducing layer and the thickness of said first stress-inducing layer.

8. The method of claim 7, further comprising determining a first target value for said first thickness and a second target value for said second thickness on the basis of an aspect ratio defined by a spacing between densely spaced one of said first transistors and densely spaced one of said second transistors.

9. The method of claim 1, wherein reducing said stress induced by said third stress-inducing layer comprises performing an ion implantation process while masking one of the first and second plurality of transistors.

10. The method of claim 8, wherein said first and second target values are approximately 100 nm and less.

11. The method of claim 10, wherein said first and second target values are approximately 80 nm and less.

12. A method, comprising:

determining a first target value for a thickness of a first stress-inducing layer to be formed above a first transistor of a first conductivity type;

determining a second target value for a thickness of a second stress-inducing layer to be formed above a second transistor of a second conductivity type other than said first conductivity type;

forming said first and second stress-inducing layers on the basis of said first and second target values, at least one of said first and second target values being less than a target thickness of stress-inducing material formed above said first and second transistors, and

forming a third stress-inducing layer above said first and second transistors on the basis of a third target value to obtain said target thickness.

13. The method of claim 12, wherein said first target value is different from said second target value.

14. The method of claim 12, further comprising removing a portion of said third stress-inducing layer from above one of said first and second transistors.

15. The method of claim 14, further comprising forming a fourth stress-inducing layer generating a different type of stress relative to said third stress-inducing layer.

16. The method of claim 15, further comprising removing a portion of said fourth stress-inducing layer from above said third stress-inducing layer.

17. The method of claim 12, further comprising selectively reducing a stress generated by said third stress-inducing layer above one of the first and second transistors.

18. The method of claim 17, wherein said stress is reduced by an ion implantation process.

19. The method of claim 12, wherein a gate length of said first and second transistors is approximately 50 nm or less.

20. The method of claim 12, wherein said first and second target values are approximately 100 nm or less.

21. The method of claim 12, wherein said first, second and third stress-inducing layers are comprised of substantially the same atomic species.

22. A semiconductor device, comprising:

a first dielectric layer formed above a first transistor, said first dielectric layer inducing a first type of stress;

a second dielectric layer formed above a second transistor, said second dielectric layer inducing a second type of stress other than said first type;

a third dielectric layer formed on said first and second dielectric layers, said third dielectric layer inducing said first type of stress above said first transistor;

said first, second and third dielectric layers comprised of substantially the same material composition.

23. The semiconductor device of claim 22, wherein said first and second transistors have a gate length of approximately 50 nm or less.

24. The semiconductor device of claim 22, wherein said first and second dielectric layers contain silicon.

25. The method of claim 24, wherein a combined thickness of said first and third dielectric layers is approximately 200 nm or less.