Closed trench MOSFET with floating trench rings as termination

• US 20080179662A1
• Filed: 01/28/2007
• Published: 07/31/2008
• Est. Priority Date: 01/28/2007
• Status: Active Grant

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Granted Patent: US 7,800,185 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the semiconductor power device further includes a source region disposed only in regions near the trenched gates in the closed N-channel MOSFET cells and away from regions near the wider trenched gate whereby a device ruggedness is improved. The source region is further disposed at a distance away from a corner or an edge of the semiconductor power device and away from a termination area. The semiconductor device further includes multiple trenched rings disposed in a termination area opposite the active area and the trenched rings having a floating voltage. The closed N-channel MOSFET cells are further supported on a red phosphorous substrate.

Claims

1. A semiconductor power device comprising:

a plurality of closed power transistor cells disposed in an active cell area on a semiconductor substrate wherein each of said transistor cells is surrounded by trenched gates constituting substantially a square or rectangular cell; and

said trenched gates further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein said semiconductor power device further comprising a source region disposed only in regions near said trenched gates in said closed power transistor cells and away from regions near said wider trenched gate whereby a device ruggedness is improved.

2. The semiconductor power device of claim 1 wherein:

said closed power transistor cells further comprising closed N-channel MOSFET cells and said source region further comprising N+ doped source region disposed only in regions near said trenched gates in said closed power transistor cells and away from regions near said wider trenched gate.

3. The semiconductor power device of claim 1 wherein:

said closed power transistor cells further comprising a body region encompassing said source region wherein said body region is extended near said trenched gate for constituting a current channel controlled by said trenched gates.

4. The semiconductor power device of claim 3 further comprising:

an insulation layer overlying said semiconductor device and a plurality of source-body contact opened through said insulation layer extending into said source region and said body region for filling with a source-body contact plug therein for electrically contacting said source region and said body region; and

a plurality of gate contact opened through said insulating layer and extending into said wider trenched gates for filling with a gate-contact plug therein for electrically contacting said wider trenched gate.

5. The semiconductor power device of claim 4 further comprising:

a patterned source metal layer and a patterned gate pad disposed on top of said insulating layer for electrically contacting said source-body contact plug and said gate-contact plugs respectively.

6. The semiconductor power device of claim 1 wherein:

said source region is further disposed at a distance away from a corner or an edge of said semiconductor power device.

7. The semiconductor power device of claim 1 wherein:

said closed power transistor cells are disposed in an active area and said source region is disposed at a distance away from a termination area opposite said active area.

8. The semiconductor power device of claim 1 wherein:

said closed power transistor cells are disposed in an active area; and

said semiconductor power device further includes a trenched ring disposed in a termination area opposite said active area and said trenched ring having a floating voltage.

9. The semiconductor power device of claim 1 wherein:

said closed power transistor cells are disposed in an active area; and

said semiconductor power device further includes multiple trenched rings disposed in a termination area opposite said active area and said trenched rings having a floating voltage.

10. The semiconductor power device of claim 1 wherein:

said closed power transistor cells further comprising closed N-channel MOSFET cells supported on a red phosphorous substrate.

11. The semiconductor power device of claim 1 further comprising:

a drain electrode disposed on a bottom surface of a semiconductor substrate supporting said semiconductor power device with said trenched gates and source region disposed near a top surface of said semiconductor substrate opposite said bottom surface.

12. A semiconductor power device comprising:

a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell;

said trenched gates further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein said semiconductor power device further comprising a source region disposed only in regions near said trenched gates in said closed N-channel MOSFET cells and. away from regions near said wider trenched gate whereby a device ruggedness is improved;

said closed power transistor cells further comprising a body region encompassing said source region wherein said body region is extended near said trenched gate for constituting a current channel controlled by said trenched gates;

an insulation layer overlying said semiconductor device and a plurality of source-body contact trenches opened through said insulation layer extending into said source region and said body region for filling with a source-body contact plug therein for electrically contacting said source region and said body region;

a patterned source metal layer disposed on top of said insulating layer for electrically contacting said source-body contact plug; and

multiple trenched rings disposed in a termination area opposite said active area and said trenched rings having a floating voltage.

13. The semiconductor power device of claim 12 wherein:

said closed N-channel MOSFET cells are further supported on a red phosphorous substrate.

14. A method of manufacturing a semiconductor power device comprising:

forming a plurality of closed power transistor cells each surrounded by trenched gates constituting substantially a square-shaped or rectangular-shaped cell in an active area and applying a source mask for covering a gate-pad area above wider trenched gates whereby source regions are formed in said closed power transistor cells in said active area and blocked from said gate pad area.

15. The method of claim 14 wherein:

said step of applying a source mask for implanting a source region further comprising a step of applying said source mask for covering a termination area opposite said active area.

16. The method of claim 14 wherein:

said step of applying a source mask for implanting a source region further comprising a step of applying said source mask for implanting said source region at a distance away from corners of edges of said semiconductor power device.

17. The method of claim 16 further comprising:

disposing a source trenched contact substantially at a center portion of said closed cell by opening a source-body contact trench in an insulation layer covering said closed semiconductor power device and extending said source-body contact trench into a source region below said insulation layer and into a body region below said source region and filling said source body contract trench with a source contact plug.

18. The method of claim 17 further comprising:

disposing a source metal layer above sad insulation layer and electrically contact said source contact plug.

19. The method of claim 14 wherein:

said step of forming said plurality of closed power transistor cells comprising a step of forming said closed power transistor cells as closed N-channel MOSFET cells on a red phosphorous substrate.

20. The method of claim 14 wherein:

said step of forming a plurality of closed power transistor cells by forming said trenched gates surrounding said closed power transistor cells further comprising a step of forming a plurality of trenched rings for connecting to a floating potential whereby a breakdown voltage of said semiconductor power device is improved.