TWO-SIDED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME

• US 20080179678A1
• Filed: 01/26/2007
• Published: 07/31/2008
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Dyer, Thomas W.
• Granted Patent: US 7,485,508 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.

Claims

1. A semiconductor structure comprising:

a buried insulator layer;

at least one first type MOSFET located on a first semiconductor layer, wherein said first semiconductor layer directly contracts a bottom surface of said buried insulator layer; and

at least one second type MOSFET located on a second semiconductor layer, wherein said second semiconductor layer directly contacts a top surface of said buried insulator layer.

2. The semiconductor structure of claim 1, further comprising:

a first middle-of-line (MOL) dielectric layer located on said at least one first type MOSFET; and

a handle wafer bonded to said first MOL dielectric layer.

3. The semiconductor structure of claim 1 wherein said first semiconductor layer and said second semiconductor layer have different surface orientations.

4. The semiconductor structure of claim 1, further comprising:

a first shallow trench isolation including a first dielectric material within said first semiconductor layer; and

a second shallow trench isolation including a second dielectric material within said second semiconductor layer, wherein said first dielectric material and said second dielectric material are different.

5. The semiconductor structure of claim 1, further comprising:

a first stress liner located directly on said at least one first type MOSFET; and

a second stress liner located directly on said at least one second type MOSFET, wherein said first stress liner and said second stress liner exert different stress to underlying structures.

6. The semiconductor structure of claim 1 wherein said first semiconductor layer and said second semiconductor layer comprise different semiconductor materials.

7. The semiconductor structure of claim 1, further comprising:

first source and drain regions of said at least one first type MOSFET that comprise a first embedded material; and

second source and drain regions of said at least one second type MOSFET that comprise a second embedded material, wherein said first embedded material is different from said second embedded material.

8. The semiconductor structure of claim 1, wherein stress applied to the channel of said at least one first type MOSFET is different from stress applied to the channel of said at least one second type MOSFET.

9. The semiconductor structure of claim 1, wherein said at least one first type MOSFET has at least one first gate electrode, said at least one second type MOSFET has at least one second gate electrode, and said at least one first gate electrode and said at least one second gate electrode comprise different materials.

10. The semiconductor structure of claim 1, further comprising an alignment structure that allows alignment of said semiconductor structure both with the top semiconductor layer on the upside of said buried insulator layer and with the bottom semiconductor layer on the upside of said buried insulator layer.

11. The semiconductor structure of claim 10, wherein said alignment structure is located in said top semiconductor layer and in said bottom semiconductor layer.

12. The semiconductor layer of claim 2, further comprising:

a second middle-of-line (MOL) dielectric layer located on said at least one second type MOSFET; and

at least one conductive via through said second MOL dielectric layer, through said second semiconductor layer, and through said buried insulator layer.

13. The semiconductor structure of claim 12, further comprising:

at least one metal wiring that contacts said at least one conductive via and said second MOL dielectric layer.

14. A method of manufacturing a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate with a carrier substrate, a buried insulator layer, and a first semiconductor layer;

forming at least one first type MOSFET on said first semiconductor layer;

forming a first middle-of-line (MOL) dielectric layer on said at least one first type MOSFET;

bonding a handle wafer on said first MOL dielectric layer;

removing a lower portion of said carrier substrate and exposing a second semiconductor layer; and

forming at least one second type MOSFET on said second semiconductor layer.

15. The method of claim 14, further comprising:

forming a second middle-of-line (MOL) dielectric layer on said at least one second type MOSFET; and

forming at least one conductive via through said second MOL dielectric layer, through said second semiconductor layer, and through said buried insulator layer.

16. The method of claim 15, further comprising forming at least one metal wiring that contacts said at least one conductive via and said second MOL dielectric layer.

17. The method of claim 14, further comprising:

forming at least one alignment mark at least within said first semiconductor layer; and

aligning said second semiconductor layer utilizing said at least one alignment mark.

18. The method of claim 14, further comprising:

providing a first stress to said at least one first type MOSFET; and

providing a second stress to said at least one second type MOSFET, wherein said first stress and said second stress are different.

19. The method of claim 14, further comprising:

forming at least one first gate electrode in said at least one first type MOSFET; and

forming at least one second gate electrode in said at least one second type MOSFET, wherein said at least one first gate electrode and at least one second gate electrode comprise different materials.

20. The method of claim 14, wherein said first semiconductor layer and said second semiconductor layer have different surface orientations.