ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE

• US 20080179679A1
• Filed: 01/31/2007
• Published: 07/31/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kolagunta, Venkat R., Shroff, Mehul D., Grudowski, Paul A.
• Granted Patent: US 7,843,011 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/3143 composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Claims

1. An electronic device comprising:

a field isolation region;

a first insulating layer having a first strain and including a first portion overlying the field isolation region, wherein, from a top view, the first portion lies entirely within the field isolation region; and

a second insulating layer having a second strain different from the first strain and including an opening wherein, from a top view, the first portion of the first insulating layer lies within the opening in the second insulating layer.

2. The electronic device of claim 1, wherein the first insulating layer and the second insulating layer include a nitride or an oxynitride.

3. The electronic device of claim 1, wherein:

the field isolation region includes;

an insulating region; and

a dummy structure;

the first insulating layer has a first edge;

the second insulating layer has a second edge; and

from a top view, the first edge and the second edge lie within the insulating region.

4. The electronic device of claim 1, further comprising:

a first active region lying immediately adjacent to the field isolation region, and including a p-channel transistor, wherein a second portion of the first insulating layer overlies the p-channel transistor; and

a second active region lying immediately adjacent to the field isolation region, and including an n-channel transistor, wherein the second insulating layer overlies the n-channel transistor.

5. The electronic device of claim 4, wherein:

the first insulating layer has a compressive strain; and

the second insulating layer has a tensile strain.

6. The electronic device of claim 4, wherein from a top view, a shortest distance from the first portion of the first insulating layer to the second portion of the first insulating layer is at least approximately 2 microns.

7. The electronic device of claim 1, wherein a quotient of a first area of the first insulating layer divided by a second area of the second insulating layer is greater than approximately 0.2.

8. An electronic device comprising:

a substrate;

an active region;

a field isolation region overlying the substrate and adjacent to the active region, wherein the field isolation region includes;

a first dummy structure including a first portion of the substrate; and

a second dummy structure including a second portion of the substrate;

a first insulating layer overlying the first dummy structure and not the second dummy structure, wherein the first insulating layer has a first strain; and

a second insulating layer overlying the second dummy structure and not the first dummy structure, wherein the second insulating layer has a second strain different from the first strain, and from a top view;

the first insulating layer lies within an opening in the second insulating layer; and

substantially none of the active region lies within the opening.

9. The electronic device of claim 8, wherein:

the first insulating layer overlies the active region; and

the active region includes a p-channel transistor.

10. The electronic device of claim 9, wherein a shortest distance from the first dummy structure to the active region is longer than a shortest distance from the second dummy structure to the active region.

11. The electronic device of claim 8, wherein from a top view, the first dummy structure lies within the opening in the second insulating layer.

12. The electronic device of claim 8, wherein from a top view:

the field isolation region further includes an insulating region surrounding the first dummy structure and the second dummy structure;

the first insulating layer has a first edge;

the second insulating layer has a second edge; and

the first edge and the second edge overlie the insulating region.

13. The electronic device of claim 8, wherein the first insulating layer and the second insulating layer have a substantially same chemical composition.

14. A process of forming an electronic device comprising:

forming a field isolation region within a substrate;

forming a first insulating layer over the field isolation region and having a first strain, wherein from a top view, an island portion of the first insulating layer lies entirely within the field isolation region; and

forming a second insulating layer over the field isolation region, having a second strain different from the first strain, and including a first opening, wherein from a top view, the island portion of the first insulating layer lies within the first opening in the second insulating layer.

15. The process of claim 14, wherein forming the island portion includes forming the island portion more than approximately 2 microns from an active region including a p-channel transistor.

16. The process of claim 14, wherein:

the first strain is a compressive strain; and

the second strain is a tensile strain.

17. The process of claim 16, wherein:

forming the first insulating layer includes using a set of precursor chemicals; and

forming the second insulating layer includes using a different set of precursor materials.

18. The process of claim 16 wherein forming the first insulating layer and forming the second insulating layer occur at different points in time.

19. The process of claim 14 further comprising:

forming a p-channel transistor prior to forming the first insulating layer; and

forming an n-channel transistor prior to forming the second insulating layer.

20. The process of claim 19, further comprising:

forming a third insulating layer over the first insulating layer and the second insulating layer;

etching a first contact opening through the third insulating layer and stopping on the first insulating layer;

etching the first insulating layer within the first opening;

etching a second contact opening through the third insulating layer and stopping on the second insulating layer;

etching the second insulating layer within the second opening;

forming a first contact within the first contact opening, wherein the first contact is electrically connected to the p-channel transistor; and

forming the second contact within the second contact opening, wherein the second contact is electrically connected to the n-channel transistor.