Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device

• US 20080179715A1
• Filed: 01/30/2007
• Published: 07/31/2008
• Est. Priority Date: 01/30/2007
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Coppa, Brian J.
• Application Number:
  US11/699,876
• Publication Number:
  US 20080179715A1
• Time in Patent Office: Days
• US Class Current: 257/647
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using a high density plasma (HDP) deposition within the trench. The second dielectric provides desirable properties such as resistance to specific etches than the first dielectric, while the first dielectric fills high aspect ratio openings more easily than the second dielectric. Depositing the first dielectric results in a decreased trench aspect ratio which must be filled by the second dielectric.

Claims

1. A method of semiconductor device fabrication, comprising:

etching a trench within a semiconductor wafer substrate assembly;

forming a first dielectric comprising atomic layer deposition (ALD) silicon dioxide within the opening;

partially etching the ALD silicon dioxide from the trench so that a first portion of the trench is filled with the ALD silicon dioxide and a second portion of the trench is unfilled with the ALD silicon dioxide; and

forming a second dielectric comprising a material different from the first dielectric within the second portion of the trench.

2. The method of claim 1 wherein the formation of the second dielectric comprises forming a high density plasma silicon dioxide.

3. The method of claim 1 wherein the formation of the second dielectric comprises forming a void-free high density plasma silicon dioxide.

4. The method of claim 1 further comprising:

densifying the ALD silicon dioxide for between about 30 and 60 minutes in a nitrogen ambient at a temperature of about 900°

C.±

100°

C.;

then

exposing the densified ALD silicon dioxide to a buffered oxide etch to partially etch the ALD silicon dioxide from the trench.

5. The method of claim 1 further comprising:

exposing the ALD silicon dioxide to MAHF to partially etch the ALD silicon dioxide from the trench;

then

densifying the ALD silicon dioxide for between about 30 and 60 minutes in a nitrogen ambient at a temperature of about 900°

C.±

100°

C.

6. The method of claim 1 further comprising etching the trench to have a width of 35 nanometers or less.

7. The method of claim 6 further comprising etching the trench to have a depth which is at least five times the width.

8. A method for forming a dielectric region for a semiconductor device, comprising:

etching a semiconductor wafer substrate assembly to have an opening therein;

forming a first dielectric within the opening using an atomic layer deposition (ALD) process such that the ALD dielectric fills a first part of the opening and leaves a second part of the opening unfilled; and

forming a second dielectric different from the first dielectric to contact the first dielectric and to fill the second part of the opening.

9. The method of claim 8 further comprising:

forming the first dielectric within the opening using the ALD process to completely fill the opening within the semiconductor wafer substrate assembly;

subjecting the first dielectric to a nitrogen ambient at a temperature of about 900°

C.±

100°

C.;

then

etching the first dielectric using a buffered oxide etch.

10. The method of claim 8 further comprising:

forming the first dielectric within the opening using the ALD process to completely fill the opening within the semiconductor wafer substrate assembly;

etching the first dielectric using MAHF;

then

subjecting the first dielectric to a nitrogen ambient at a temperature of about 900°

C.±

100°

C.

11. The method of claim 8 further comprising forming the opening in the semiconductor wafer substrate assembly to have a width of 35 nm or less.

12. The method of claim 11 further comprising forming the opening in the semiconductor wafer substrate assembly to have a depth which is at least five times the width.

13. A method of semiconductor device fabrication, comprising:

etching a trench within a semiconductor wafer substrate assembly;

forming an atomic layer deposition (ALD) dielectric within the trench using a process comprising;

exposing the etched semiconductor wafer substrate assembly to a silicon-based compound and to at least one of a heterocyclic aromatic organic compound and a Lewis base;

then

exposing the etched semiconductor wafer substrate assembly to a compound containing oxygen and to at least one of a heterocyclic aromatic organic compound and a Lewis base;

etching the ALD dielectric such that the ALD dielectric fills only a first portion of the trench to a and leaves a second portion of the trench unfilled by the ALD dielectric; and

filling the second part of the trench using a dielectric different from the ALD dielectric.

14. The method of claim 13 further comprising filling the second part of the trench using high density plasma (HDP) oxide.

15. The method of claim 13 further comprising:

densifying the ALD dielectric;

then

etching the ALD dielectric with a buffered oxide etch;

then

filling the second part of the trench using the dielectric different from the ALD dielectric.

16. The method of claim 13 further comprising:

etching the ALD dielectric with MAHF;

then

densifying the ALD dielectric;

then

filling the second part of the trench using the dielectric different from the ALD dielectric.

17. The method of claim 13 further comprising flowing the silicon-based compound and the at least one of heterocyclic aromatic organic compound and Lewis base at flow rates sufficient to maintain a pressure within a deposition chamber to between about 100 mtorr and about 400 torr.

18. The method of claim 13 further comprising flowing the compound containing oxygen and hydrogen and the heterocyclic aromatic organic compound at flow rates sufficient to maintain a pressure within a deposition chamber to between about 100 mtorr and about 400 torr.

19. A semiconductor device comprising:

a trench formed within a semiconductor wafer substrate assembly;

a first dielectric which fills a majority of the trench, wherein the first dielectric comprises atomic layer deposition (ALD) oxide; and

a second dielectric different from the ALD oxide which fills a remainder of the trench.

20. The semiconductor device of claim 19 further comprising:

first and second transistor gates comprising gate or tunnel oxide, wherein the ALD oxide is subjacent and between the first and second transistor gates;

the ALD oxide being formed to a level below a level of the gate or tunnel oxide;

the second dielectric being formed at least partially directly between the first and second transistor gates.

21. The method of claim 20 further comprising:

etching a portion of the gate or tunnel oxide at a location;

then

regrowing gate or tunnel oxide at the location.

22. The semiconductor device of claim 20 wherein the second dielectric comprises high density plasma oxide.

23. A method of semiconductor device fabrication, comprising:

etching a shallow isolation trench within a semiconductor wafer substrate assembly;

forming a first dielectric comprising tetraethyl orthosilicate (TEOS) within the opening using a chemical vapor deposition (CVD) process or a low-pressure CVD (LPCVD) process;

partially etching the TEOS from the trench so that a first portion of the trench is filled with the TEOS and a second portion of the trench is unfilled with the TEOS; and

forming a second dielectric comprising a material different from the first dielectric within the second portion of the trench to form shallow trench isolation within the semiconductor wafer substrate assembly.

24. The method of claim 23 wherein the formation of the second dielectric comprises forming a high density plasma silicon dioxide.