Method of Phase Noise Reduction in a Soi Type Master-Slave Circuit

• US 20080180152A1
• Filed: 03/11/2005
• Published: 07/31/2008
• Est. Priority Date: 03/29/2004
• Status: Abandoned Application

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Desortiaux, Vincent
• Application Number:
  US11/547,548
• Publication Number:
  US 20080180152A1
• Time in Patent Office: Days
• US Class Current: 327/203
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their floating body is set to a potential by means of an appropriate connection, in order to locally reduce their contribution to the overall phase noise of said circuit. It also provides a reduced phase noise master-slave circuit. This circuit includes floating body SOI type transistors, characterised in that the potential of said floating body of the transistors that (60, 61) contribute to said phase noise is set by means of an appropriate connection (64, 65).

Claims

1-21. -21. (canceled)

22. A method for designing an electronic circuit with reduced noise phase comprising a master section and a slave section, said sections comprising a plurality of floating body SOI type transistors, comprising:

selecting the or each floating body transistor which contributes to phase noise degradation,

setting the floating body of said or each said located transistor to a potential by means of a connection, in order to locally reduce its contribution to the overall phase noise of said circuit.

23. A method according to claim 22, wherein said selection step comprising searching for the or each transistor associated with the slave section and which switches from a conducting or on-state to a blocked or off-state, or vice versa, during the transfer of a data signal from an input to an output of said slave section.

24. A method according to claim 23, wherein that selection step selects only the or each transistor which is located on the electric path followed by said data signal.

25. A method according to claim 22, wherein the floating body of at least one switching transistor is connected to an electrical source of the type selected from a voltage source and a current source.

26. A method according to claim 22, wherein the floating body of at least one transistor is connected to a polarization circuit.

27. A method according to claim 22, wherein the floating body of at least one transistor is connected to a node of the circuit.

28. A method according to claim 27, wherein said node is a gate, a drain or a source of a transistor.

29. A method according to claim 28, wherein each floating body of a transistor is connected to the gate, the drain, or the source thereof.

30. A method according to claim 22, wherein said connection comprises a floating body contact.

31. An electronic circuit comprising a master section and slave section, said circuit comprising a plurality of floating body SOI type transistors, wherein the potential of the floating body of at least one transistor identified as contributing to phase noise is set by means of a connection, whereby the phase noise of the circuit is reduced.

32. A circuit according to claim 31, wherein said at least one transistor is located in the slave section.

33. A circuit according to claim 32, wherein said at least one transistor is a transistor which switches from a conducting or on-state to a blocked or off-state, or vice versa, during the transfer of a data signal from an input to an output of said slave section.

34. A circuit according to claim 33, wherein said at least one transistor is located on the electrical path of said data signal.

35. A circuit according to claim 34, wherein the floating body of at least one switching transistor is connected to an electrical source of the type selected from a voltage source and a current source.

36. A circuit according to claim 33, wherein the floating body of at least one transistor is connected to a node of the circuit.

37. A circuit according to claim 36, wherein the node is a gate, a drain or a source of a transistor.

38. A circuit according to claim 37, wherein the floating body of at least one transistor is connected to the gate, the drain or the source thereof.

39. A circuit according to claim 31, wherein said connection comprises a floating body contact.

40. A circuit according claim 31, wherein each of said master and slave sections is a latch circuit, said circuit being a bistable trigger circuit.

41. A simulation file containing a set of structured data representative of a master section and slave section circuit with low phase noise, said circuit comprising floating body SOI type transistors, wherein said data include data for connecting the floating body of certain transistors previously identified as contributing to the phase noise to a node with an appropriate potential.

42. A simulation file for manufacturing an electronic circuit with reduced phase noise, said circuit comprising a master section and a slave section each comprising a plurality of floating body SOI type transistors, said simulation file containing a set of structured data representative of said circuit, wherein said data include data representative of a connection between the floating body of certain transistors, previously identified as contributing to the phase noise, and a node with an appropriate bias.