FLASH MEMORY SYSTEM CAPABLE OF IMPROVING ACCESS PERFORMANCE AND ACCESS METHOD THEREOF

• US 20080181008A1
• Filed: 03/29/2007
• Published: 07/31/2008
• Est. Priority Date: 01/25/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-Kwon, Lee, Byeong-Hoon, Kim, Ki-Hong, Lee, Seung-Won
• Application Number:
  US11/693,106
• Publication Number:
  US 20080181008A1
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification

Abstract

A flash memory system capable of improving an access performance and an access method thereof. The system includes: a flash memory device including a plurality of storage regions; a contents memory storing setting information corresponding to the plurality of storage regions, respectively; and a processing unit setting operation conditions of the flash memory device by referring to the setting information during an access operation for the flash memory device.

Claims

1. A system comprising:

a flash memory device including a plurality of storage regions;

a contents memory storing setting information corresponding to the plurality of storage regions, respectively; and

a processing unit setting operation conditions of the flash memory device by referring to the setting information during an access operation for the flash memory device.

2. The system of claim 1, wherein the flash memory device is a NAND flash memory.

3. The system of claim 2, wherein the plurality of storage regions is in page units.

4. The system of claim 3, wherein the setting information comprises one of a program parameter, an erase parameter, and a read parameter for one page unit.

5. The system of claim 4, wherein the program parameter comprises one of information such as a program start voltage, a step width, a level of a program voltage, and a number of program loops for one page unit.

6. The system of claim 4, wherein the erase parameter comprises a size of a bulk voltage that is applied when an erase operation is performed.

7. The system of claim 4, wherein the read parameter comprises a size of a word line voltage that is applied when a read operation is performed.

8. The system of claim 1, wherein the contents memory is a non-volatile memory.

9. The system of claim 8, wherein the processing unit detects a mode of the access operation and reads the setting information corresponding to the detected mode from the contents memory.

10. The system of claim 9, wherein the processing unit performs a control operation for performing one of a read operation and a write operation by referring to the setting information.

11. The system of claim 10, wherein the processing unit updates the setting information in the contents memory after the access operation.

12. The system of claim 1, further comprising a control register temporarily storing the setting information read from the contents memory.

13. The system of claim 12, wherein the setting information are parameters corresponding to at least one storage region in the plurality of storage regions, the at least one storage region being accessed during the access operation.

14. The system of claim 1, wherein the flash memory device, the contents memory, and the processing unit are embedded devices and are embedded on a single chip.

15. An access method for a flash memory device including a plurality of storage regions, the method comprising:

detecting an access mode;

reading setting information corresponding to the access mode; and

setting operation conditions of the flash memory device according to the setting information.

16. The method of claim 15, wherein the access mode is a program operation mode writing data into the flash memory device.

17. The method of claim 16, wherein the setting information corresponding to the program operation mode comprises at least one of information such as a program start voltage, a step size of a program pulse, a number of program loops, and a size of a verify voltage.

18. The method of claim 15, wherein the access mode is a read operation mode reading data programmed in the flash memory device.

19. The method of claim 18, wherein the setting information corresponding to the read operation mode comprises information of a voltage supplied to a selected word line during the reading of the programmed data.

20. The method of claim 15, wherein the access mode is an erase operation mode erasing data programmed in the flash memory device.

21. The method of claim 20, wherein the setting information corresponding to the erase operation mode comprises at least one of bulk voltage information applied during the erase operation and size information of a word line voltage.

22. The method of claim 15, further comprising accessing the flash memory device according to the access mode when the setting of the operation conditions is completed in the flash memory device.

23. The method of claim 22, further comprising updating the setting information according to the accessing operation.

24. The method of claim 15, wherein the setting information is stored in non-volatile memory separated from the flash memory device.

25. The method of claim 15, wherein the flash memory device is a NAND flash memory.

26. The method of claim 25, wherein the plurality of storage regions correspond to a page unit.

27. The method of claim 25, wherein the plurality of storage regions correspond to a block unit.

28. The method of claim 15, wherein the flash memory device is an embedded NAND flash memory device.

29. A system comprising:

a flash memory device including a plurality of storage regions;

a processing unit setting operation conditions of the flash memory device by referring to the setting information corresponding to the respective plurality of storage regions during an access operation for the flash memory device.

30. The system of claim 29, wherein the setting information corresponding to the plurality of storage regions is stored in the contents memory.