SEMICONDUCTOR MEMORY DEVICE WITH REFRESH TRIGGER

• US 20080181017A1
• Filed: 08/27/2007
• Published: 07/31/2008
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Tatsuya, WATANABE, Hiroshi
• Granted Patent: US 7,609,576 B2
• Time in Patent Office: Days
• US Class Current: 365/185.25
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, an X decoder designating a position of an X axis of the memory cell, a Y decoder designating a position of a Y axis crossing the X axis, a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder, a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source, and a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cell transistors;

an X decoder designating a position of an X axis of the memory cell;

a Y decoder designating a position of a Y axis crossing the X axis;

a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder;

a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source; and

a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information.

2. The device according to claim 1, wherein an operation of the device comprises the steps of:

initializing the semiconductor time switch by the controller in a power on state to set the lifetime of the semiconductor time switch;

leaving the semiconductor time switch in a power off state after said initializing;

reading an output signal of the semiconductor time switch in the power on state after said leaving;

by checking a difference between the output signal in the power on state and an output signal at said initializing, issue, through the refresh trigger circuit, a refresh signal “

0”

when the difference is within a predetermined offset, or issue a refresh signal “

1”

when the difference is out of the predetermined offset.

3. The device according to claim 2, wherein the controller transfers information stored in one area of the memory cell array to other area thereof to refresh the information when the refresh signal is “

1”

in the power on state.

4. The device according to claim 2, wherein the lifetime of the semiconductor time switch set in said initializing is shorter than a data retention time of the memory cell transistor in association with the semiconductor time switch.

5. The device according to claim 2, wherein the output signal of the semiconductor time switch changes between before and after the lifetime set in said initializing.

6. The device according to claim 1, wherein at said refreshing the information, the semiconductor time switch is re-initialized.

7. The device according to claim 1, wherein the semiconductor time switch and the memory cell transistor are embedded in the same chip, and each has a floating gate.

8. The device according to claim 1, wherein a capacity of the information before said refreshing is equal to a capacity of the information after said refreshing.

9. The device according to claim 1, wherein, when N is set as an arbitrary natural number and a capacity of the information stored is set as N bits, the N bits are assigned to non-continuous addresses on the memory cell array.

10. The device according to claim 1, wherein a block including addresses recording the information is transferred to and rewritten in another block as a whole.

11. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cell transistors;

an X decoder designating a position of an X axis of the memory cell;

a Y decoder designating a position of a Y axis crossing the X axis;

a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder;

a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source;

a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information; and

an operational amplifier receiving a refresh signal from the refresh trigger circuit, and making operations of read, write and erase of the memory cell transistors.

12. The device according to claim 11, wherein an operation of the device comprises the steps of:

initializing the semiconductor time switch by the operational amplifier in a power on state to set the lifetime of the semiconductor time switch;

leaving the semiconductor time switch in a power off state after said initializing;

reading an output signal of the semiconductor time switch in the power on state after said leaving;

by checking a difference between the output signal in the power on state and an output signal at said initializing, issue, through the refresh trigger circuit, a refresh signal “

0”

when the difference is within a predetermined offset, or issue a refresh signal “

1”

when the difference is out of the predetermined offset.

13. The device according to claim 12, wherein the controller transfers information stored in one area of the memory cell array to other area thereof when the refresh signal is “

1”

in the power on state.

14. The device according to claim 12, wherein the lifetime of the semiconductor time switch set in said initializing is shorter than a data retention time of the memory cell transistor associated with the semiconductor time switch.

15. The device according to claim 12, wherein the output signal of the semiconductor time switch changes between before and after the lifetime set in said initializing.

16. The device according to claim 11, wherein at said refreshing the information, the semiconductor time switch is re-initialized.

17. The device according to claim 11, wherein the semiconductor time switch and the memory cell transistor are embedded in the same chip, and each has a floating gate.

18. The device according to claim 11, wherein a capacity of the information before said refreshing is equal to a capacity of the information after said refreshing.

19. The device according to claim 11, wherein, when N is set as an arbitrary natural number and a capacity of the information stored is set as N bits, the N bits are assigned to non-continuous addresses on the memory cell array.

20. The device according to claim 11, wherein a block including addresses recording the information is transferred to and rewritten in another block as a whole.