Intra-device RF bus and control thereof

• US 20080181186A1
• Filed: 01/31/2007
• Published: 07/31/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Granted Patent: US 8,064,826 B2
• Time in Patent Office: Days
• US Class Current: 370/338
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90

Abstract

A device includes a first integrated circuit, a second integrated circuit and an RF bus controller. Each of the first and second ICs includes a radio frequency (RF) bus transceiver. The RF bus controller is coupled to control intra-device RF communications between the RF bus transceivers of the first and second ICs.

Claims

1. A device comprises:

a first integrated circuit (IC) having a first radio frequency (RF) bus transceiver;

a second IC having a second RF bus transceiver; and

an RF bus controller coupled to control intra-device RF communications between the first and second RF bus transceivers.

2. The device of claim 1, wherein the intra-device RF communications comprises at least one of:

RF data communications;

RF instruction communications;

RF control signal communications; and

RF input/output communications.

3. The device of claim 1 further comprises:

an RF communication path to facilitate the intra-device RF communications, wherein the RF communication path is at least one of a waveguide, a dielectric layer of a supporting structure, and free space.

4. The device of claim 3, wherein the RF bus controller further functions to:

select one of the waveguide RF communication path, the dielectric layer RF communication path, or the free space RF communication path based on at least one aspect of one of the intra-device RF communications.

5. The device of claim 1, wherein the intra-device RF communications comprises:

an RF interrupt request communication; and

an RF interrupt acknowledgement communication, wherein the first IC includes a processing module and the second IC includes an asynchronous circuit module, and wherein the asynchronous circuit module provides an interrupt request to the processing module as the RF interrupt request communication and the processing module provides an interrupt acknowledgement as the RF interrupt acknowledgement communication.

6. The device of claim 1 further comprises at least one of:

the first IC including the RF bus controller; and

the second IC including the RF bus controller.

7. The device of claim 1, wherein the intra-device RF communications comprises at least one of:

operating system level communications; and

application level communications.

8. The device of claim 1 further comprises at least one of:

a wireline serial link coupling the RF bus controller to first and second ICs, wherein the RF bus controller receives RF bus access request via the wireline serial link from the first or second IC and provides access to an RF bus to the first or second IC via the wireline serial link; and

a wireless interface, wherein the RF bus controller receives the RF bus access request via the wireless interface from the first or second IC and provides access to the RF bus to the first or second IC via the wireless interface.

9. The device of claim 8, wherein each of the first and second ICs comprises:

a first RF transceiver that operates within a first frequency band, wherein the intra-device RF communications occur within the first frequency band; and

a second RF transceiver that operates within a second frequency band to communicate with the RF bus controller via the wireless interface.

10. The device of claim 8, wherein the RF bus controller further functions to:

allocate at least one communication slot to the wireless interface; and

allocate at least one other communication slot for the intra-device RF communications, wherein the at least one communication slot and the at least one other communication slot are time division multiple access (TDMA) slots, frequency division multiple access (FDMA) slots, or code division multiple access (CDMA) slots.

11. A device comprises:

a plurality of integrated circuits (ICs), wherein each IC of the plurality of ICs includes a plurality of circuit modules, wherein each circuit module of the plurality of circuit modules includes a radio frequency (RF) bus transceiver; and

an RF bus controller coupled to control intra-IC RF communications between a circuit module of the plurality of circuit modules of different ICs of the plurality of ICs and to control inter-IC RF communications between first and second circuit modules of the plurality of circuit modules of one of the plurality of ICs.

12. The device of claim 11, wherein the intra-IC RF communications and the inter-IC RF communications comprises at least one of:

RF data communications;

RF instruction communications;

RF control signal communications; and

RF input/output communications.

13. The device of claim 11, wherein the intra-IC RF communications comprises:

an RF interrupt request communication; and

an RF interrupt acknowledgement communication, wherein one of the plurality of circuit modules of a first IC of the plurality of ICs includes a processing module and one of the plurality of circuit modules of a second IC of the plurality of ICs includes an asynchronous circuit module, and wherein the asynchronous circuit module provides an interrupt request to the processing module as the RF interrupt request communication and the processing module provides an interrupt acknowledgement as the RF interrupt acknowledgement communication.

14. The device of claim 11, wherein the inter-IC RF communications comprises:

an RF interrupt request communication; and

an RF interrupt acknowledgement communication, wherein one of the plurality of circuit modules of a first IC of the plurality of ICs includes a processing module and another one of the plurality of circuit modules of the first IC includes an asynchronous circuit module, and wherein the asynchronous circuit module provides an interrupt request to the processing module as the RF interrupt request communication and the processing module provides an interrupt acknowledgement as the RF interrupt acknowledgement communication.

15. The device of claim 11 further comprises:

one of the plurality of ICs including the RF bus controller.

16. The device of claim 11, wherein the intra-IC RF communications and the inter-IC RF communications comprises at least one of:

operating system level communications; and

application level communications.

17. The device of claim 11 further comprises at least one of:

a wireline serial link coupling the RF bus controller to the plurality of ICs, wherein the RF bus controller receives RF bus access request via the wireline serial link from one of the plurality of ICs and provides access to an RF bus to the one of the plurality of ICs via the wireline serial link; and

a wireless interface, wherein the RF bus controller receives the RF bus access request via the wireless interface from the one of the plurality of ICs and provides access to the RF bus to the one of the plurality of ICs via the wireless interface.

18. The device of claim 17, wherein the RF bus controller comprises at least one of:

a first RF transceiver that operates within a first frequency band, wherein the intra-IC RF communications and the inter-IC RF communications occur within the first frequency band, wherein the RF bus controller allocates at least one communication slot to the wireless interface, allocates at least one other communication slot for the intra-IC RF communications, and allocates at least another communication slot for the inter-IC RF communications, wherein the at least one communication slot, the at least one other communication slot, and the at least another communication slot are time division multiple access (TDMA) slots, frequency division multiple access (FDMA) slot, or code division multiple access (CDMA) slots; and

a second RF transceiver that operates within a second frequency band.

19. The device of claim 17, wherein the RF bus controller comprises at least one of:

a first RF transceiver that operates within a first frequency band, wherein the intra-IC RF communications occur within the first frequency band and the inter-IC RF communications occur within a second frequency band, wherein the RF bus controller allocates at least one communication slot in the first frequency band to the first RF transceiver and allocates at least one other communication slot in the first frequency band for the intra-IC RF communications, wherein the at least one communication slot in the first frequency band and the at least one other communication slot in the first frequency band are time division multiple access (TDMA) slots, frequency division multiple access (FDMA) slot, or code division multiple access (CDMA) slots; and

a second RF transceiver that operates within the second frequency band, wherein the RF bus controller allocates at least one communication slot in the second frequency band to the second RF transceiver and allocates at least one other communication slot in the second frequency band for the inter-IC RF communications, wherein the at least one communication slot in the second frequency band and the at least one other communication slot in the second frequency band are TDMA slots, FDMA slot, or CDMA slots.

20. The device of claim 17, wherein the RF bus controller comprises:

a RF transceiver that operates within a first frequency band, wherein the intra-IC RF communications occur within the second frequency band and the inter-IC RF communications occur within a third frequency band.

21. A device comprises:

a processing core having a processing core radio frequency (RF) bus transceiver;

a memory system having a memory system RF bus transceiver;

a peripheral interface module, wherein the peripheral interface module includes a peripheral RF bus transceiver and interfaces with a plurality of peripheral circuits; and

an RF bus controller coupled to control access to an RF input/output bus among the plurality of peripheral circuits and the peripheral interface module and coupled to control access to an RF memory bus among the processing core, the memory system, and the peripheral interface module.

22. The device of claim 21, wherein the plurality of peripheral circuits comprises at least two of:

a hard disk drive;

a compact disk (CD) drive;

a digital video disk (DVD) drive;

a video card;

an audio card;

a wireline network card; and

a wireless network card.

23. The device of claim 21 further comprises:

the RF input/output bus supporting at least one of;

RF peripheral data communications, RF peripheral instruction communications, and RF peripheral control signal communications; and

the RF memory bus supporting at least one of;

RF memory data communications, RF memory instruction communications, and RF memory control signal communications.

24. The device of claim 23, wherein the RF peripheral control signal communications comprises:

an RF interrupt request communication; and

an RF interrupt acknowledgement communication.

25. The device of claim 21, wherein the RF memory bus supports:

RF operating system level communications; and

RF application level communications.

26. The device of claim 21 further comprises at least one of:

a wireline serial link coupling the RF bus controller to the processing core, the memory system, and the peripheral interface module, wherein the RF bus controller receives RF bus access request via the wireline serial link from one of the processing core, the memory system, and the peripheral interface module and provides access to the RF input/output bus or to the RF memory bus to the one of the processing core, the memory system, and the peripheral interface module via the wireline serial link; and

a wireless interface, wherein the RF bus controller receives the RF bus access request via the wireless interface from the one of the processing core, the memory system, and the peripheral interface module and provides access to the RF input/output bus or to the RF memory bus to the one of the processing core, the memory system, and the peripheral interface module via the wireless interface.