MULTI-NETWORK SHARED PHY LAYER

• US 20080181249A1
• Filed: 07/27/2007
• Published: 07/31/2008
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Karaoguz, Jeyhan
• Granted Patent: US 8,149,867 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04W 88/00 Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices

Abstract

A system and method for providing PHY layer signal processing in a PHY layer signal processing circuit, at least portions of which may be shared for communication with a plurality of different types of communication networks. Various aspects of the present invention may, for example and without limitation, provide a PHY layer signal processing module that operates to perform a PHY layer signal processing operation on an input PHY layer signal. The PHY layer signal processing module may, for example, operate in a first operating mode to process the input PHY layer signal in a first manner in accordance with a first communication protocol. The PHY layer signal processing module may also, for example, operate in a second operating mode to process the input PHY layer signal in a second manner in accordance with a second communication protocol.

Claims

1. A physical (“

PHY”

) layer signal processing circuit for utilization in a communication system, the PHY layer signal processing circuit comprising;

a PHY layer signal processing module that operates primarily to perform a PHY layer signal processing operation on an input PHY layer signal, where the PHY layer signal processing module operates to, at least;

receive the input PHY layer signal;

if the received input PHY layer signal is associated with a first communication protocol, then;

perform the PHY layer signal processing operation on the received input PHY layer signal by operating in a first operating mode, the first operating mode associated with performing the PHY layer signal processing operation on a PHY layer signal associated with the first communication protocol; and

output the processed PHY layer signal; and

if the received input PHY layer signal is associated with a second communication protocol, different from the first communication protocol, then;

perform the PHY layer signal processing operation on the received input PHY layer signal by operating in a second operating mode, the second operating mode different from the first operating mode and associated with performing the PHY layer signal processing operation on a PHY layer signal associated with the second communication protocol; and

output the processed PHY layer signal.

2. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a control input that receives a control signal indicative of an operating mode in which the PHY layer signal processing module is to operate to process the input PHY layer signal.

3. The PHY layer signal processing circuit of claim 1, further comprising:

a second PHY layer signal processing module that operates primarily to perform a second PHY layer signal processing operation on a signal received from the PHY layer signal processing module in a first manner; and

a third PHY layer signal processing module, substantially independent of the second PHY layer signal processing module, that operates primarily to perform the second PHY layer signal processing operation on a signal received from the PHY layer signal processing module in a second manner different from the first manner.

4. The PHY layer signal processing circuit of claim 1, further comprising:

a second PHY layer signal processing module that operates primarily to perform a second PHY layer signal processing operation on an input signal in a first manner and output a processed signal to the PHY layer signal processing module; and

a third PHY layer signal processing module, substantially independent of the second PHY layer signal processing module, that operates primarily to perform the second PHY layer signal processing operation on an input signal in a second manner and output a processed signal to the PHY layer signal processing module, the second manner different from the first manner.

5. The PHY layer signal processing circuit of claim 1, further comprising a Multiple-Input-Multiple-Output (“

MIMO”

) Radio Frequency (“

RF”

) transceiver module, communicatively coupled to the PHY layer signal processing module, that operates to perform MIMO RF processing on a received input PHY layer signal by operating in a first operating mode in accordance with the first communication protocol, and operates to perform MIMO RF processing on a received input PHY layer signal by operating in a second mode in accordance with the second communication protocol.

6. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a Fast Fourier Transform (“

FFT”

) engine that operates in a first operating mode to perform FFT processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform FFT processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

7. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a MIMO processor that operates in a first operating mode to perform MIMO demodulation and/or equalization processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform MIMO demodulation and/or equalization processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

8. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a Viterbi decoder that operates in a first operating mode to perform Viterbi decoding on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform Viterbi decoding on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

9. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a symbol mapper that operates in a first operating mode to perform symbol mapping on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform symbol mapping on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

10. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a convolutional encoder that operates in a first operating mode to perform convolutional encoding on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform convolutional encoding on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

11. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a MIMO stream processor that operates in a first operating mode to perform MIMO parsing, interleaving and/or mapping on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform MIMO parsing, interleaving and/or mapping on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

12. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises an Inverse FFT (“

IFFT”

) engine that operates in a first operating mode to perform IFFT processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform IFFT processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

13. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises at least one of an I-Q modulator, upsampler, transmit filter and/or upconverter that operates in a first operating mode to perform signal processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform signal processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

14. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises an Analog-to-Digital Converter (“

ADC”

) that operates in a first operating mode to perform ADC processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform ADC processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

15. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module comprises a Digital-to-Analog Converter (“

DAC”

) that operates in a first operating mode to perform DAC processing on the received input PHY layer signal in a first manner in accordance with the first communication protocol, and operates in a second operating mode to perform DAC processing on the received input PHY layer signal in a second manner in accordance with the second communication protocol.

16. The PHY layer signal processing circuit of claim 1, wherein the first communication protocol is a WiFi communication protocol, and the second communication protocol is a WiMAX communication protocol.

17. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module utilizes substantially the same circuitry to operate in the first operating mode and to operate in the second operating mode.

18. The PHY layer signal processing circuit of claim 1, wherein the PHY layer signal processing module operates in the first operating mode and the second operating mode sequentially and not in parallel.

19. The PHY layer signal processing circuit of claim 1, where the PHY layer signal processing circuit is a baseband processor.

20. In a PHY layer signal processing circuit of a communication system, a method for performing PHY layer signal processing on a PHY layer signal, the method comprising:

receiving an input PHY layer signal at a first PHY layer signal processing module that operates primarily to perform a first PHY layer signal processing operation on an input PHY layer signal;

if the received input PHY layer signal is associated with a first communication protocol, then processing, at the first PHY layer signal processing module, the received input PHY layer signal in a first manner by, at least in part, operating the first PHY layer signal processing module in a first operating mode; and

if the received input PHY layer signal is associated with a second communication protocol, different from the first communication protocol, then processing, at the first PHY layer signal processing module, the received input PHY layer signal in a second manner different from the first manner by, at least in part, operating the first PHY layer signal processing module in a second operating mode different from the first operating mode; and

outputting the processed PHY layer signal from the first PHY layer signal processing module.

21. The method of claim 20, further comprising determining whether the received input PHY layer signal is associated with the first communication protocol by, at least in part, analyzing the received input PHY layer signal.

22. The method of claim 20, further comprising:

receiving a control signal; and

determining whether the received input PHY layer signal is associated with the first communication protocol by, at least in part, analyzing the received control signal.

23. The method of claim 20, further comprising:

if the received input PHY layer signal is associated with the first communication protocol, then;

receiving, at a second PHY layer signal processing module, a second PHY layer signal comprising the PHY layer signal output from the first PHY layer signal processing module, where the second PHY layer signal processing module operates primarily to perform a second PHY layer signal processing operation in a first manner; and

processing, at the second PHY layer signal processing module, the second PHY layer signal by, at least in part, performing the second PHY layer signal processing operation on the second PHY layer signal in the first manner; and

if the received input PHY layer signal is associated with the second communication protocol, then;

receiving, at a third PHY layer signal processing module, a third PHY layer signal comprising the PHY layer signal output from the first PHY layer signal processing module, where the third PHY layer signal processing module operates primarily to perform the second PHY layer signal processing operation in a second manner, different from the first manner; and

processing, at the third PHY layer signal processing module, the third PHY layer signal by, at least in part, performing the second PHY layer signal processing operation on the third PHY layer signal in the second manner.

24. The method of claim 20, further comprising:

if the received input PHY layer signal is associated with the first communication protocol, then;

receiving, at a second PHY layer signal processing module, a second PHY layer signal, where the second PHY layer signal processing module operates primarily to perform a second PHY layer signal processing operation in a first manner;

processing, at the second PHY layer signal processing module, the second PHY layer signal by, at least in part, performing the second PHY layer signal processing operation on the second PHY layer signal in the first manner; and

outputting the processed second PHY layer signal to the first PHY layer signal processing module; and

if the received input PHY layer signal is associated with the second communication protocol, then;

receiving, at a third PHY layer signal processing module, a third PHY layer signal, where the third PHY layer signal processing module operates primarily to perform the second PHY layer signal processing operation in a second manner, different from the first manner;

processing, at the third PHY layer signal processing module, the third PHY layer signal by, at least in part, performing the second PHY layer signal processing operation on the third PHY layer signal in the second manner; and

outputting the processed third PHY layer signal to the first PHY layer signal processing module.

25. The method of claim 20, wherein the first communication protocol is a WiFi communication protocol, and the second communication protocol is a WiMAX communication protocol.

26. The method of claim 20, wherein operating the first PHY layer signal processing module in the first operating mode and operating the first PHY layer signal processing module in the second operating mode both comprise utilizing substantially the same circuitry of the first PHY layer signal processing module.

27. The method of claim 20, wherein the first PHY layer signal processing module operates in the first and second operating modes sequentially and not in parallel.

28. The method of claim 20, where the PHY layer signal processing circuit is a baseband processor.