Phosphorus Containing Si Epitaxial Layers in N-Type Source/Drain Junctions

• US 20080182075A1
• Filed: 12/17/2007
• Published: 07/31/2008
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ye, Zhiyuan, Kim, Yihwan, Chopra, Saurabh
• Granted Patent: US 7,960,236 B2
• Time in Patent Office: Days
• US Class Current: 428/172
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: Y10T 428/24612 Composite web or sheet

Abstract

Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.

Claims

1. A method for epitaxially forming a silicon film on a substrate surface, comprising:

placing a substrate including a monocrystalline surface and secondary surfaces into a process chamber;

exposing the substrate to a deposition gas comprising a mix of a silicon source, a carrier gas and an n-type dopant source at a temperature of below about 600°

C.; and

creating an epitaxial silicon layer with an n-dopant with a level equal to or greater than about 7×

10²⁰ atoms cm<sup>−

3</sup>.

2. The method as claimed in claim 1, wherein the pressure in the process chamber is maintained at about 10 Torr.

3. The method of claim 1, wherein the n-dopant is phosphorus.

4. The method of claim 3, wherein the n-type dopant source comprises phosphine.

5. The method of claim 1, wherein the silicon source is a higher order silane.

6. The method of claim 5, wherein the silicon source is selected from trisilane, pentasilane and mixtures thereof.

7. The method of claim 1, wherein the level of the n-dopant is at least about 8×

10²⁰ atoms/cm³.

8. The method of claim 1, wherein the level of the n-dopant is about 1.2×

10²¹ atoms/cm³.

9. The method of claim 1, wherein the temperature during deposition is in a range of about 540°

C. and below about 560°

C.

10. The method of claim 1, wherein the epitaxial silicon layer with the n-dopant is a capping layer on top of a silicon carbon layer.

11. The method of claim 1, wherein the epitaxial layer has a tensile stress created by n-dopants in the layer that is equivalent to the tensile stress that can be created by a concentration of substitutional carbon in the epitaxial layer of about 0.55%.

12. The method of claim 1, wherein a measured resistivity in the epitaxial layer is greater than about 0.25 mOhm·

cm and lower than 0.5 mOhm·

cm.

13. The method of claim 1, wherein the epitaxial film is formed during a fabrication step of a transistor manufacturing process, and the method further comprises:

forming a gate dielectric on a substrate;

forming a gate electrode on the gate dielectric; and

forming source/drain regions on the substrate on opposite sides of the electrode and defining a channel region between the source/drain regions.

14. The method of claim 13, wherein the epitaxial silicon layer with the n-dopant is a layer formed on recessed source/drain areas.

15. The method of claim 13, wherein the epitaxial silicon layer with the n-dopant is a capping layer on top of a silicon carbon layer formed on recessed source/drain areas.

16. A silicon film on a substrate surface, comprising an epitaxially formed silicon layer, the layer including an n-dopant with a concentration being not less than about 7×

10²⁰ atoms/cm³.

17. The silicon film as claimed in claim 16, wherein the n-dopant is phosphorus.

18. The silicon film as claimed in claim 17, wherein the concentration of phosphorus is about 1×

10²¹ atoms/cm³.

19. The silicon film as claimed in claim 16, wherein a measured resistivity is greater than about 0.25 mOhm·

cm and lower than 0.5 mOhm·

cm.

20. The silicon film as claimed in claim 16, wherein the layer also includes substitutional carbon.

21. The silicon film as claimed in claim 16, wherein the epitaxially formed silicon layer has a tensile stress created by n-dopants in the layer that is equivalent to the tensile stress that can be created by a concentration of substitutional carbon in the epitaxially formed silicon layer of about 0.55%.

22. The silicon film as claimed in claim 16, wherein the epitaxially formed silicon layer with n-dopant is a layer formed on recessed source/drain areas.

23. The silicon film as claimed in claim 16, wherein the epitaxially formed silicon layer with n-dopant is a capping layer on top of a silicon carbon layer formed on recessed source/drain areas.