Mask pattern of semiconductor device and manufacturing method thereof

• US 20080182181A1
• Filed: 07/20/2007
• Published: 07/31/2008
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Lee, Jun Seok
• Granted Patent: US 7,803,504 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

Provided is a mask pattern of a semiconductor device. The mask pattern includes a plurality of main patterns and a plurality of assistance patterns. The main patterns are adjacent to one another. The assistance pattern is disposed on at least one of an end portion and a middle portion of each of the main patterns and has a line width greater than that of the main pattern. The assistance patterns are staggered.

Claims

1. A mask pattern, the mask pattern comprising:

a plurality of main patterns adjacent to one another; and

a plurality of staggered assistance patterns on each of the main patterns, the assistance pattern having a line width greater than a minimum width.

2. The mask pattern according to claim 1, wherein each main pattern comprises:

a first pattern; and

a plurality of second patterns having a line width less than that of the first pattern and extending from the first pattern,

wherein the assistance patterns are on the second patterns.

3. The mask pattern according to claim 2, wherein the first patterns are parallel, and the second patterns are staggered relative to second patterns of an adjacent first pattern.

4. The mask pattern according to claim 2, wherein the assistance patterns have a line width greater than that of the second patterns.

5. The mask pattern according to claim 1, wherein a ratio of a height to a width of the main pattern is three or more.

6. The mask pattern according to claim 2, wherein a ratio of a height to a width of the first patterns is three or more.

7. A method of manufacturing a mask pattern, the method comprising:

forming a plurality of adjacent main patterns; and

forming an assistance pattern on each of the main patterns, the assistance pattern having a line width greater than a minimum width.

8. The method according to claim 7, wherein the assistance patterns are staggered.

9. The method according to claim 7, wherein each of the main patterns comprises:

a first pattern; and

a plurality of second patterns having line widths less than that of the first pattern and extending from the first pattern,

wherein the assistance patterns are on the second patterns.

10. The method according to claim 9, wherein the first patterns are parallel, and the second patterns are staggered relative to second patterns of an adjacent first pattern.

11. The method according to claim 7, wherein forming the main patterns comprises:

cutting a middle portion of the main pattern to overlap the cut main patterns; and

adjusting a size of an overlapped portion of the cut main patterns,

wherein forming the assistance patterns comprises forming the assistance pattern at the overlapped portion.

12. The method according to claim 8, wherein forming the main patterns comprises placing the assistance patterns at an end of in a middle portion of each second pattern.

13. The method according to claim 12, further comprising cutting each second pattern to create a plurality of ends in each second pattern.

14. The method according to claim 11, wherein each assistance pattern has a line width greater than that of the second patterns.

15. The method according to claim 7, wherein a ratio of a height to a width of the main pattern is three or more.

16. The method according to claim 8, wherein a ratio of a height to a width of the first patterns is three or more.