Abstracting a multithreaded processor core to a single threaded processor core

• US 20080184233A1
• Filed: 01/30/2007
• Published: 07/31/2008
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kim, Hyun, Norton, Scott J.
• Granted Patent: US 9,003,410 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 2209/5021 Priority
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5005 to service a request
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

Claims

1. A method to abstract a multithreaded processor core to single threaded processor core, the method comprising:

viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and

viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

2. The method of claim 1, wherein the first hardware thread has a first identifier and the second hardware thread has a second identifier, and wherein the first identifier and the second identifier are translated into a third identifier that is viewed by the user application.

3. The method of claim 1, further comprising:

exposing an identifier of the single CPU object by use of a function call.

4. The method of claim 1, further comprising:

running an application on the first hardware thread or the second hardware thread if the application performs an application-to-processor binding request to the single CPU object.

5. The method of claim 1, further comprising:

returning attributes of the core in response to a call to the single CPU object.

6. The method of claim 1, further comprising:

returning utilization of the core in response to a call to the single CPU object.

7. The method of claim 1, further comprising:

disabling the second hardware thread if the first hardware thread is executing a software thread of a real-time application.

8. The method of claim 1, further comprising:

setting an application-level attribute in an application to permit the application to view each hardware thread in the core.

9. The method of claim 1, further comprising:

executing, by the second hardware thread, a low priority software thread.

10. The method of claim 1, further comprising:

executing, by the first hardware thread, a high priority software thread.

11. The method of claim 1, further comprising:

preventing a software application thread that is executing in the kernel to be scheduled on the second hardware thread.

12. The method of claim 1, further comprising:

scheduling a next highest priority software application thread.

13. The method of claim 1, further comprising:

scheduling only low priority software threads to consume core resources during a CPU idle time while the first hardware thread is servicing cache misses.

14. An apparatus for abstracting a multithreaded processor core to single threaded processor core, the apparatus comprising:

a computer system including a processor and an operating system, wherein the operating system views a first hardware thread and a second hardware thread in a core of the processor; and

wherein a user application views the first hardware thread and the second hardware thread as a single CPU object.

15. The apparatus of claim 14, wherein the first hardware thread has a first identifier and the second hardware thread has a second identifier, and wherein the first identifier and the second identifier are translated into a third identifier that is viewed by the user application.

16. The apparatus of claim 14, wherein an identifier of the single CPU object is exposed by use of a function call.

17. The apparatus of claim 14, wherein an application runs on the first hardware thread or the second hardware thread if the application performs an application-to-processor binding request to the single CPU object.

18. The apparatus of claim 14, wherein attributes of the core are returned in response to a call to the single CPU object.

19. The apparatus of claim 14, wherein utilization of the core are returned in response to a call to the single CPU object.

20. The apparatus of claim 14, wherein the second hardware thread is disabled if the first hardware thread is executing a software thread of a real-time application.

21. The apparatus of claim 14, wherein an application-level attribute in an application is set to permit the application to view each hardware thread in the core.

22. The apparatus of claim 14, wherein the second hardware thread executes a low priority software thread.

23. The apparatus of claim 14, wherein the first hardware thread executes a high priority software thread.

24. The apparatus of claim 14, wherein a software application thread that is executing in the kernel is prevented to be scheduled on the second hardware thread.

25. The apparatus of claim 14, wherein a next highest priority software application thread is scheduled.

26. The apparatus of claim 14, wherein only low priority software threads are scheduled to consume core resources during a CPU idle time while the first hardware thread is servicing cache misses.

27. An apparatus for abstracting a multithreaded processor core to single threaded processor core, the apparatus comprising:

means for viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and

means for viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

28. An article of manufacture comprising:

a machine-readable medium having stored thereon instructions to;

view, by an operating system, a first hardware thread and a second hardware thread in a processor core; and

view, by a user application, the first hardware thread and the second hardware thread as a single CPU object.