ELECTROSTATIC MEMBRANES FOR SENSORS, ULTRASONIC TRANSDUCERS INCORPORATING SUCH MEMBRANES, AND MANUFACTURING METHODS THEREFOR

• US 20080184549A1
• Filed: 02/05/2008
• Published: 08/07/2008
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Aime Flesch, An Nguyen-Dinh, Nicolas Felix
• Original Assignee: Aime Flesch, An Nguyen-Dinh, Nicolas Felix
• Inventors: Flesch, Aime, Felix, Nicolas, NGUYEN-DINH, An
• Granted Patent: US 7,770,279 B2
• Time in Patent Office: Days
• US Class Current: 29/594
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: Y10T 29/49005 Acoustic transducer
• CPC Class Codes: Y10T 29/49007 Indicating transducer
• CPC Class Codes: Y10T 29/4908 Acoustic transducer
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A micro-machined ultrasonic transducer substrate for immersion operation is formed by a particular arrangement of a plurality of micro-machined membranes that are supported on a silicon substrate. The membranes, together with the substrate, form surface microcavities that are vacuum sealed to provide electrostatic cells. The cells can operate at high frequency and can cover a broader bandwidth in comparison with conventional piezoelectric bulk transducers.

Claims

1. A method for making capacitive micromachined ultrasonic transducer devices for ultrasonic transducer use, said method comprising:

providing a silicon wafer substrate;

depositing a silicon oxide layer on a top surface of said substrate so as to provide dielectric insulation between the substrate and further components;

providing a bottom electrode on the silicon oxide layer;

providing a sacrificial layer over the bottom electrode, said sacrificial layer being comprised of a high lateral etching rate columnar structured oxide;

providing a low stress silicon nitride membrane on said sacrificial layer using a low pressure chemical vapor deposition process;

removing sacrificial material from selected sites of said sacrificial layer to form cavities for cells;

depositing an oxide layer as a sealing material using a physical vapor deposition process and under vacuum conditions so as to preserve said cavities; and

providing a top electrode layer over said silicon nitride membrane.

2. A method according to claim 1 wherein the silicon substrate comprises a highly doped silicon material permitting the bottom electrode to be provided externally of the substrate.

3. A method according to claim 1 wherein the bottom electrode comprises doped polysilicon metal.

4. A method according to claim 1 wherein the bottom electrode comprises metal.

5. A method according to claim 1 wherein the steps of providing said membrane and providing said bottom electrode and said top electrode layer are repeated to provide a multilayered membrane structure.

6. A method according to claim 1 wherein the bottom electrode is formed in a predetermined pattern that minimizes parasitic capacitance effects.

7. A method according to claim 5 wherein said bottom electrode is of a shape similar to that of the top electrode and is provided in front of said top electrode.

8. A method according to claim 1 wherein the silicon substrate comprises a SOI material.

9. A method according to claim 1 wherein said method is interrupted at an intermediate stage prior to forming of said cavities for cells, and said method further comprises providing at least one complementary element on said substrate at said intermediate stage so as to reduce the risk of membrane damage during handling.

10. A method according to claim 9 wherein said at least one element comprises at least one component selected from the group consisting of inductive components, capacitive components, and active components.

11. A method according to claim 9 wherein said at least one element comprises an element performing a signal conditioning function.