Memory Device

• US 20080185578A1
• Filed: 01/23/2008
• Published: 08/07/2008
• Est. Priority Date: 02/02/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Harima, Noriko, Yoshizumi, Kensuke
• Granted Patent: US 9,006,741 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The nanoparticle includes a conductive material coated with an organic film. The first portion is in contact with the first conductive layer and the second conductive layer, and a side surface of the first portion is surrounded by the second portion.

Claims

1. A memory device comprising:

a first conductive layer;

a second conductive layer; and

a memory layer interposed between the first conductive layer and the second conductive layer, wherein;

the memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle including a conductive material coated with an organic film,

the first conductive layer is electrically connected to the second conductive layer through the first portion,

the first portion is in contact with the first conductive layer and the second conductive layer, and

a side surface of the first portion is surrounded by the second portion.

2. The memory device according to claim 1, wherein a grain size of the nanoparticle is greater than or equal to 1 nm and less than or equal to 200 nm.

3. The memory device according to claim 1, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material.

4. The memory device according to claim 1, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material, and one of a reducing agent, a binder, and a plasticizer.

5. The memory device according to claim 1, wherein the first portion is one of columnar and subulate in shape.

6. The memory device according to claim 1, wherein the first portion is in contact with the second portion.

7. The memory device according to claim 1, wherein the first portion is not in contact with the second portion.

8. The memory device according to claim 1, further comprising a layer, wherein the layer is interposed between the memory layer and one of the first conductive layer and the second conductive layer, and wherein the layer is one of an insulating layer and a semiconductor layer.

9. A memory device comprising:

a first conductive layer;

a second conductive layer;

a memory layer interposed between the first conductive layer and the second conductive layer, and

a transistor electrically connected to a memory element including the first conductive layer, the second conductive layer, and the memory layer, wherein;

the memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle including a conductive material coated with an organic film,

the first conductive layer is electrically connected to the second conductive layer through the first portion,

the first portion is in contact with the first conductive layer and the second conductive layer, and

a side surface of the first portion is surrounded by the second portion.

10. The memory device according to claim 9, wherein a grain size of the nanoparticle is greater than or equal to 1 nm and less than or equal to 200 nm.

11. The memory device according to claim 9, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material.

12. The memory device according to claim 9, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material, and one of a reducing agent, a binder, and a plasticizer.

13. The memory device according to claim 9, wherein the first portion is one of columnar and subulate in shape.

14. The memory device according to claim 9, wherein the first portion is in contact with the second portion.

15. The memory device according to claim 9, wherein the first portion is not in contact with the second portion.

16. The memory device according to claim 9, further comprising a layer, wherein the layer is interposed between the memory layer and one of the first conductive layer and the second conductive layer, and wherein the layer is one of an insulating layer and a semiconductor layer.

17. A memory device comprising:

a first conductive layer;

a second conductive layer; and

a memory layer interposed between the first conductive layer and the second conductive layer, wherein;

the memory layer includes a first portion and a second portion, each of which includes nanoparticles each including a conductive material coated with an organic film,

the nanoparticles included in the first portion are welded,

the first portion is in contact with the first conductive layer and the second conductive layer, and

a side surface of the first portion is surrounded by the second portion.

18. The memory device according to claim 17, wherein a grain size of the nanoparticle is greater than or equal to 1 nm and less than or equal to 200 nm.

19. The memory device according to claim 17, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material.

20. The memory device according to claim 17, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material, and one of a reducing agent, a binder, and a plasticizer.

21. The memory device according to claim 17, wherein the first portion is one of columnar and subulate in shape.

22. The memory device according to claim 17, wherein the first portion is in contact with the second portion.

23. The memory device according to claim 17, wherein the first portion is not in contact with the second portion.

24. The memory device according to claim 17, further comprising a layer, wherein the layer is interposed between the memory layer and one of the first conductive layer and the second conductive layer, and wherein the layer is one of an insulating layer and a semiconductor layer.

25. A memory device comprising:

a first conductive layer;

a second conductive layer;

a memory layer interposed between the first conductive layer and the second conductive layer, and

a transistor electrically connected to a memory element including the first conductive layer, the second conductive layer, and the memory layer, wherein;

the memory layer includes a first portion and a second portion, each of which includes nanoparticles each including a conductive material coated with an organic film,

the nanoparticles included in the first portion are welded,

the first portion is in contact with the first conductive layer and the second conductive layer, and

a side surface of the first portion is surrounded by the second portion.

26. The memory device according to claim 25, wherein a grain size of the nanoparticle is greater than or equal to 1 nm and less than or equal to 200 nm.

27. The memory device according to claim 25, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material.

28. The memory device according to claim 25, wherein the organic film includes one of a surfactant, and a material forming a coordinate bond with the conductive material, and one of a reducing agent, a binder, and a plasticizer.

29. The memory device according to claim 25, wherein the first portion is one of columnar and subulate in shape.

30. The memory device according to claim 25, wherein the first portion is in contact with the second portion.

31. The memory device according to claim 25, wherein the first portion is not in contact with the second portion.

32. The memory device according to claim 25, further comprising a layer, wherein the layer is interposed between the memory layer and one of the first conductive layer and the second conductive layer, and wherein the layer is one of an insulating layer and a semiconductor layer.