Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors
First Claim
1. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
- multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and
,a series resistor temporarily connected in series to said second electrodes, wherein said series resistor is configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements.
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Accused Products
Abstract
Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
9 Citations
20 Claims
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1. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
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multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and
,a series resistor temporarily connected in series to said second electrodes, wherein said series resistor is configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
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multiple parallel memory elements, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes; and
,series resistors electrically connected in series to corresponding first electrodes of said memory elements, wherein said series resistors are configured to limit current passing through said memory elements during a simultaneous conditioning process of said transition metal oxide in each of said memory elements. - View Dependent Claims (9, 10, 11)
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12. A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
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forming a series resistor over said memory elements such that said series resistor contacts said second electrodes of said memory elements; simultaneously applying current to said memory elements so as to simultaneously condition said transition metal oxide in each of said memory elements, wherein said series resistor limits said current passing through said memory elements to avoid damaging said transition metal oxide; and removing said series resistor. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
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forming series resistors within said memory cells such that said series resistors are electrically connected to said first electrodes of said memory elements; and simultaneously applying current to said memory elements so as to simultaneously condition said transition metal oxide in each of said memory elements, wherein said series resistors limit said current passing through said memory elements to avoid damaging said transition metal oxide. - View Dependent Claims (20)
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Specification