METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE

• US 20080186052A1
• Filed: 02/01/2007
• Published: 08/07/2008
• Est. Priority Date: 02/01/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Needham, Thomas D., Ranck, Andrew R.
• Granted Patent: US 8,407,658 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA speed, and writing the PLD programming data to a data buffer. The method also includes reading the PLD programming data from the data buffer, and transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

Claims

1. A method for using direct memory access (DMA) to initialize a programmable logic device (PLD), the method comprising:

manipulating a control line of the PLD to configure the PLD in a programming mode;

receiving PLD programming data from a DMA control at a DMA speed;

writing the PLD programming data to a data buffer;

reading the PLD programming data from the data buffer; and

transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

2. The method of claim 1 further comprising:

configuring the DMA control to read the PLD programming data from a non-volatile memory device (NVM); and

using a processor to start the DMA control reading the PLD programming data from the NVM.

3. The method of claim 1 further comprising:

using at least one of a processor and the DMA control to initiate manipulating the control line of the PLD to configure the PLD in the programming mode via a configuration and status register.

4. The method of claim 1 further comprising:

providing an alternative path to transmit the PLD programming data to a programming port on the PLD via a configuration and status register; and

writing the PLD programming data to the configuration and status register.

5. The method of claim 1, wherein a data word width of the PLD programming data written to the data buffer is modified when the PLD programming data is read from the data buffer.

6. The method of claim 1, wherein a byte ordering of the PLD programming data written to the data buffer is modified when the PLD programming data is read from the data buffer.

7. The method of claim 1 further comprising:

reading a status of the PLD to verify successful programming of the PLD with the PLD programming data.

8. The method of claim 1 further comprising:

blocking access to the programming port on the PLD when the PLD is not in the programming mode.

9. An integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD, the IC comprising:

an input/output (I/O) interface, the I/O interface converting a signal format between the IC and the PLD; and

a PLD interface, the PLD interface including;

a configuration and status register, the configuration and status register adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface;

a data buffer, the data buffer for temporarily holding PLD programming data received from a DMA control at a DMA speed; and

pacing logic, the pacing logic controlling the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

10. The IC of claim 9 further comprising:

a DMA control, the DMA control operably coupled to the PLD interface.

11. The IC of claim 10, wherein the DMA control is operably coupled to a non-volatile memory device (NVM), the NVM storing the PLD programming data.

12. The IC of claim 11 further comprising the NVM.

13. The IC of claim 11 further comprising:

a processor, the processor operably coupled to the PLD interface and the DMA control, and wherein the processor performs a method, the method comprising;

writing a value to the configuration and status register of the PLD interface, the value utilized for manipulating the control line of the PLD via the I/O interface to configure the PLD in a programming mode;

configuring the DMA control to read the PLD programming data from the NVM;

initiating the DMA control to start reading the PLD programming data from the NVM; and

reading the configuration and status register of the PLD interface to verify successful programming of the PLD with the PLD programming data.

14. The IC of claim 9, wherein the PLD interface modifies at least one of a data word width and a byte ordering of the PLD programming data written to the data buffer when the PLD programming data is read from the data buffer.

15. The IC of claim 9, wherein access to the programming port on the PLD is blocked when the PLD is not in the programming mode.

16. The IC of claim 9, wherein the PLD interface further includes a bus selector, the bus selector adapted to provide access to the configuration and status register for a processor and the DNA control;

and

wherein the configuration and status register is adapted to transmit the PLD programming data to a programming port on the PLD via the I/O interface.

17. A method for initializing a programmable logic device (PLD), the method comprising:

manipulating a control line of the PLD to configure the PLD in a programming mode;

selecting a PLD programming data source from at least one of a DMA control and a processor;

receiving PLD programming data from the selected data source; and

transmitting the PLD programming data to a programming port on the PLD.

18. The method of claim 17, wherein the manipulating a control line of the PLD to configure the PLD in a programming mode is commanded by at least one of the DMA control and the processor.

19. The method of claim 17, wherein receiving PLD programming data from the selected data source is received by at least one of a data buffer and a configuration and status register.

20. The method of claim 17 further comprising:

configuring the DMA control to read the PLD programming data from a non-volatile memory device (NVM); and

using the processor to start the DMA control reading the PLD programming data from the NVM.

21. The method of claim 20, further comprising:

writing the PLD programming data to a data buffer; and

reading the PLD programming data from the data buffer.

22. The method of claim 17 further comprising:

blocking access to the programming port on the PLD when the PLD is not in the programming mode.

23. A system for using direct memory access (DMA) to initialize a programmable logic device (PLD), the system comprising:

the PLD including a programming port with a control line, the PLD on an assembly; and

an integrated circuit (IC) operably coupled to the programming port of the PLD, the IC on the assembly, and including;

an input/output (I/O) interface, the I/O interface converting a signal format between the IC and the PLD; and

a PLD interface, the PLD interface including;

a configuration and status register, the configuration and status register adapted to manipulate the control line of the programming port of the PLD via the I/O interface;

a data buffer, the data buffer for temporarily holding PLD programming data received from a DMA control at a DMA speed; and

pacing logic, the pacing logic controlling the speed of transmitting the PLD programming data to the programming port on the PLD via the I/O interface at a PLD programming speed.

24. The system of claim 23 further comprising:

a DMA control, the DMA control operably coupled to the PLD interface.

25. The system of claim 24, wherein the DMA control is operably coupled to a non-volatile memory device (NVM), the NVM storing the PLD programming data.

26. The system of claim 25, wherein the NVM is located external to the assembly.

27. The system of claim 25 further comprising:

a processor, the processor operably coupled to the PLD interface and the DMA control, and wherein the processor performs a method, the method comprising;

writing a value to the configuration and status register of the PLD interface, the value utilized for manipulating the control line of the PLD via the I/O interface to configure the PLD in a programming mode;

configuring the DMA control to read the PLD programming data from the NVM;

initiating the DMA control to start reading the PLD programming data from the NVM; and

reading the configuration and status register of the PLD interface to verify successful programming of the PLD with the PLD programming data.

28. The system of claim 23, wherein the PLD interface modifies at least one of a data word width and a byte ordering of the PLD programming data written to the data buffer when the PLD programming data is read from the data buffer;

and

wherein access to the programming port on the PLD is blocked when the PLD is not in a programming mode.

29. The system of claim 24 further comprising:

multiple assemblies operably coupled to the DMA control through the PLD interface of each IC on each of the multiple assemblies; and

wherein the DMA control is located external to the multiple assemblies.

30. A computer program product for supporting using direct memory access (DMA) to initialize a programmable logic device (PLD), the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method comprising;

manipulating a control line of the PLD to configure the PLD in a programming mode;

receiving PLD programming data from a DMA control at a DMA speed; and

transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

31. The computer program product of claim 30 further comprising:

configuring the DMA control to read the PLD programming data from a non-volatile memory device (NVM).

32. The computer program product of claim 30, further comprising:

writing the PLD programming data to a data buffer;

reading the PLD programming data from the data buffer; and

wherein a data word width of the PLD programming data written to the data buffer is modified when the PLD programming data is read from the data buffer.

33. The computer program product of claim 30, wherein a byte ordering of the PLD programming data is modified prior to transmitting the PLD programming data to a programming port on the PLD.

34. The computer program product of claim 30 further comprising:

reading a status of the PLD to verify successful programming of the PLD with the PLD programming data.

35. The computer program product of claim 30 further comprising:

blocking access to the programming port on the PLD when the PLD is not in the programming mode.