LEVEL SHIFTER FOR GATE DRIVER
First Claim
1. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, and each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:
- a first node and a second node;
a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal;
a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the first node;
a charge/discharge circuit, for receiving an input signal and a control signal, and coupled to the second node;
a threshold voltage detector, for receiving the control signal, and coupled to the first node and the source of the driving transistor; and
a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor.
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Accused Products
Abstract
A level shifter for a gate driver has a driving transistor, a reset transistor, a charge/discharge circuit, a threshold voltage detector, and a memory capacitor. An initial threshold voltage of the driving transistor is detected by the threshold voltage detector, and then memorized in the memory capacitor. The charge/discharge circuit charges or discharges the capacitor, and receives a control signal to actuate the level shifter. The reset transistor receives an output signal of a next stage level shifter as a reset signal, so as to restore the initial status of the level shifter. In this way, the driving current output from the level shifter is irrelevant to the threshold voltage of the driving transistor.
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Citations
27 Claims
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1. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, and each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:
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a first node and a second node; a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal; a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the first node; a charge/discharge circuit, for receiving an input signal and a control signal, and coupled to the second node; a threshold voltage detector, for receiving the control signal, and coupled to the first node and the source of the driving transistor; and a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:
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a first node and a second node; a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source is coupled to an output signal; a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the second node; a charge/discharge circuit, for receiving an input signal and a control signal, and coupled to a high-potential voltage, a second low-potential voltage, and the second node; a threshold voltage detector, for receiving the control signal, and coupled to the first node and the source of the driving transistor; and a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:
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a first node and a second node; a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal; a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the first node; a charge/discharge circuit, used for receiving an input signal, a first control signal, and a second control signal, and coupled to a second low-potential voltage and the second node; a threshold voltage detector, used for receiving the first control signal and the second control signal, and coupled to the first node and the source of the driving transistor; and a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:
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a first node and a second node; a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal; a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a low-potential voltage, and the drain is, coupled to the first node; a charge circuit, for receiving an input signal, and coupled to the second node; a threshold voltage detector, for receiving the control signal, and coupled to the first node, the second node, and the source of the driving transistor; and a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor. - View Dependent Claims (25, 26, 27)
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Specification