VERSATILE Si-BASED PACKAGING WITH INTEGRATED PASSIVE COMPONENTS FOR mmWAVE APPLICATIONS

• US 20080186247A1
• Filed: 04/04/2008
• Published: 08/07/2008
• Est. Priority Date: 08/03/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Grzyb, Janusz, Knickerbocker, John Ulrich, Cotte, John Michael, Magerlein, John Harold, Pfeiffer, Ullrich R., Gaucher, Brian Paul, Liu, Duixian, Jahnes, Christopher Vincent, Patel, Chirag Suryakant, Hoivik, Nils Deneke
• Granted Patent: US 7,808,798 B2
• Time in Patent Office: Days
• US Class Current: 343/841
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package

Abstract

An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Claims

1. An apparatus comprising:

an interposer comprising a substrate having an upper and lower surface, said upper surface having at least one cavity for forming a portion of an antenna structure, said interposer including conducting through vias from said upper surface to said lower surface, said conducting through vias at said lower surface adapted for coupling to a source of electrical signals and a voltage supply,

a top Si part having interconnection wiring on a lower surface and having first pads for electrically mounting an integrated circuit chip thereon,

said top Si part having second pads on said lower surface mating with a plurality of conducting through vias at said upper surface of said interposer, and having an antenna positioned over said cavity for forming said antenna structure at times said top Si part is mated with said interposer.

2. The apparatus of claim 1, wherein said interposer has at least one cavity for receiving an integrated circuit chip and wherein said first pads are positioned so that said integrated circuit chip is positioned in said cavity when said top Si part is mated with said interposer.

3. The apparatus of claim 2, wherein said interposer and said top Si part are bonded together to form a perimeter seal around at least said integrated circuit chip.

4. The apparatus of claim 1, wherein at least one of said at least one cavities has a bottom surface coated with a conductor.

5. The apparatus of claim 1, wherein at least one of said at least one cavities has a bottom surface and a plurality of sidewalls coated with a conductor.

6. The apparatus of claim 2, wherein said at least one cavity for receiving an integrated circuit chip has a plurality of sidewalls coated with a conductor to provide shielding from said antenna structure.

7. The apparatus of claim 5, wherein said at least one cavity for receiving an integrated circuit chip has a plurality of sidewalls coated with a conductor.

8. The apparatus of claim 1, further including a mirco electro mechanical (MEMs) device positioned on said top Si part and coupled between said integrated circuit chip and said antenna structure.

9. The apparatus of claim 1, wherein said integrated circuit chip has rf electrical signals with frequencies in the range from 1 to 100 GHz.

10. The apparatus of claim 1, wherein said interposer is selected from the group consisting of Si and quartz.

11. The apparatus of claim 10, wherein said top Si part is selected from the group consisting of Si and quartz whereby a thermal coefficient of expansion of said top Si part matches a thermal coefficient of expansion of said interposer.

12. The apparatus of claim 1, wherein said top Si part includes a region of dielectric material extending from said lower surface to an upper surface over a portion of said antenna structure to enhance proper antenna performance.

13. The apparatus of claim 1, wherein said top Si part includes a region of dielectric material shaped to form a lens over said antenna structure to focus the antenna signal propagation.

14. The apparatus of claim 1, wherein said cavity has a flat bottom surface tilted at an angle with respect to said upper surface of said interposer.

15. The apparatus of claim 1, wherein said cavity has a curved bottom surface to focus the antenna signal propagation.

16. The apparatus of claim 1, wherein said antenna comprises two spaced apart electrodes increasing in space therebetween from one end to the other to provide antenna signal propagation away from said spaced apart electrodes where said spacing is greatest in the plane of said electrodes.

17. The apparatus of claim 3, wherein said perimeter seal is a metal to metal hermetic seal.

18. The apparatus of claim 17, wherein said perimeter seal extends around the edge of said upper surface of said interposer.

19. The apparatus of claim 1, wherein said interconnection wiring comprises a plurality of layers, said layers comprised of dielectric and metal conductors, said layers spaced apart and interconnected by vias.

20. The apparatus of claim 1, further including a plurality of cavities for forming respective portions of a plurality of antenna structures, a plurality of antennas, a plurality of integrated circuit chips, and a plurality of interconnection wiring.