Timing controller, liquid crystal display device having the same, and method of operating a timing controller
First Claim
Patent Images
1. A timing controller comprising:
- a line memory block receiving and storing pixel data received at a first data transfer frequency, and outputting the stored pixel data at a second data transfer frequency; and
a control unit, which is connected to an output terminal of the line memory block, transferring pixel data output from the line memory block to an external frame memory at the second data transfer frequency and outputting pixel data, which is transferred from the frame memory, after converting the pixel data to a predetermined data format.
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Abstract
In a timing controller and a liquid crystal display device having the same, the timing controller includes a line memory block receiving and storing pixel data received at a first data transfer frequency, and outputting the stored pixel data at a second data transfer frequency. A control unit, which is connected to an output terminal of the line memory block, transfers pixel data output from the line memory block to an external frame memory at the second data transfer frequency and outputting pixel data, which is transferred from the frame memory, after converting the pixel data to a predetermined data format.
15 Citations
16 Claims
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1. A timing controller comprising:
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a line memory block receiving and storing pixel data received at a first data transfer frequency, and outputting the stored pixel data at a second data transfer frequency; and a control unit, which is connected to an output terminal of the line memory block, transferring pixel data output from the line memory block to an external frame memory at the second data transfer frequency and outputting pixel data, which is transferred from the frame memory, after converting the pixel data to a predetermined data format. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A timing controller comprising:
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a first line memory block storing pixel data on an Nth horizontal line of a liquid crystal panel received by a first data transfer frequency, wherein N is a natural number; a second line memory block storing pixel data on an (N+1)th horizontal line of the liquid crystal panel received by the first data transfer frequency; a selection block, which is connected to input terminals of the first and the second line memory block, outputting pixel data received from an external source to the first line memory block or the second line memory block in response to a line memory selection signal; a control unit, connected to output terminals of the first and the second line memory blocks, transferring pixel data output from the first and the second line memory blocks to a frame memory at a second data transfer frequency, converting pixel data output from the frame memory to a predetermined data format, and outputting the converted pixel data; a data format conversion unit converting pixel data output from the control unit to a data format corresponding to a driving method of the liquid crystal panel; and a control signal generator generating a plurality of control signals driving the liquid crystal panel in response to a control signal output from the control unit. - View Dependent Claims (10, 11, 12)
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13. An operating method of a timing controller comprising:
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outputting pixel data received at a selection circuit at a first data transfer frequency to a first line memory block or a second line memory block in response to a line memory selection signal; the first line memory block storing pixel data on an Nth, where N is a natural number, horizontal line of a liquid crystal panel among the pixel data received at the first data transfer frequency; the second line memory block storing pixel data on an (N+1)th horizontal line of the liquid crystal panel among the pixel data received at the first data transfer frequency; and transferring pixel data output from the first and the second line memory blocks with an external frame memory at a second data transfer frequency at a control unit, which is connected to an output terminal of the first and the second line memory block respectively. - View Dependent Claims (14, 15, 16)
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Specification