SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME

• US 20080186776A1
• Filed: 02/06/2008
• Published: 08/07/2008
• Est. Priority Date: 02/07/2007
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: PYEON, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 7,952,929 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

Claims

1. A method for programming a NAND flash string having a source line select device, memory cells and a string select device connected in series between a bitline and a source line, comprising:

biasing the bitline to one of a first supply voltage level and a second supply voltage level;

asymmetrically precharging groupings of channels corresponding to the memory cells to different voltage levels from the source line for setting a selected memory cell channel to a program inhibit state independent of background data stored in unselected memory cells; and

programming the selected memory cell only when the bitline is biased to the second supply voltage level, the selected memory cell remaining in the program inhibit state when the bitline is biased to the first supply voltage level.

2. The method of claim 1, wherein programming the selected memory cell includes driving the string select device to the first supply voltage level for coupling the bitline to the selected memory cell only when the bitline is biased to the second supply voltage level.

3. The method of claim 1, wherein asymmetrically precharging includes biasing the source line to a string precharge voltage .

4. The method of claim 1, wherein asymmetrically precharging includes coupling the source line to the memory cells by driving the source line select device to a source line pass voltage .

5. The method of claim 4, wherein asymmetrically precharging includes

precharging a lower channel corresponding to the memory cells between the source line select device and a first memory cell adjacent to the selected memory cell to a first precharge voltage, the lower channel including the selected memory cell and a second memory cell adjacent to the selected memory cell,

precharging an intermediate channel corresponding to the first memory cell to a second precharge voltage, and

precharging an upper channel corresponding to the memory cells between the first memory cell and the string select device to a third precharge voltage.

6. The method of claim 5, wherein precharging the lower channel includes driving the gate terminals of the memory cells between the source line select device and the first memory cell to a first pass voltage.

7. The method of claim 6, wherein precharging the intermediate channel includes driving the gate terminal of the first memory cell to a second pass voltage, the second pass voltage being at least 0V.

8. The method of claim 7, wherein the second pass voltage is greater than a programmed memory cell threshold voltage and less than the pass voltage.

9. The method of claim 8, wherein precharging the upper channel includes driving the gate terminals of the memory cells between the first memory cell and the string select device to the first pass voltage.

10. The method of claim 9, wherein the upper channel is boosted by a difference between the first pass voltage and the second pass voltage to provide the third precharge voltage.

11. The method of claim 10, wherein the second pass voltage is selected to be a value for turning off the first memory cell when the upper channel is at the third precharge voltage.

12. The method of claim 11, wherein precharging the lower channel further includes

turning off the second memory cell, and

turning off the source line select device.

13. The method of claim 12, wherein precharging the lower channel further includes locally boosting the selected memory cell channel to a voltage effective for inhibiting programming by driving the gate of the selected memory cell to a programming voltage.

14. The method of claim 13, wherein the programming voltage is greater than the first pass voltage the string precharge voltage and the source line pass voltage, and the string precharge voltage is at least the source line pass voltage.

15. The method of claim 4, wherein the string precharge voltage and the source line pass voltage are at the first pass voltage.

16. The method of claim 1, wherein at least one of the memory cells between the selected memory cell and the source line select device corresponds to a programmed page, the at least one of the memory cells having one of a programmed threshold voltage and an erased threshold voltage.

17. The method of claim 5, wherein the first memory cell corresponds to a programmed page having one of the programmed threshold voltage and the erased threshold voltage.

18. The method of claim 1, wherein the memory cells between the selected memory cell and the source line select device correspond to erased pages having an erased threshold voltage.

19. The method of claim 1, wherein the memory cells between the selected memory cell and the string select device correspond to erased pages having an erased threshold voltage.

20. A method for programming a NAND flash string having a source line select device, memory cells and a string select device connected in series between a bitline and a source line, comprising:

biasing the bitline to one of a first supply voltage level and a second supply voltage level;

precharging groupings of channels corresponding to the memory cells to different voltage levels from the source line for turning off a first memory cell adjacent to a selected memory cell;

precharging the selected memory cell channel to a program inhibit state in response to an applied programming voltage; and

,

driving the string select device to the first supply voltage level for coupling the bitline to the selected memory cell only when the bitline is biased to the second supply voltage level, the selected memory cell remaining in the program inhibit state when the bitline is biased to the first supply voltage level.

21. A method for programming a NAND flash string having a source line select device, memory cells and a string select device connected in series between a bitline and a source line comprising:

driving all wordlines to a first pass voltage for coupling a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage;

continuing driving all the wordlines except a first wordline corresponding to a first memory cell adjacent to a selected memory cell to a second pass voltage greater than the first pass voltage, the first memory cell being positioned between the selected memory cell and the string select device;

driving a second wordline corresponding to a second memory cell adjacent to the selected memory cell to a first supply voltage for turning off the second memory cell;

driving a third wordline corresponding to the selected memory cell to a programming voltage greater than the second pass voltage; and

,

coupling the bitline to the selected memory cell.

22. The method of claim 21, wherein coupling the string precharge voltage includes driving the source line select device to a source line pass voltage.

23. The method of claim 21, wherein coupling the bitline includes driving the string select device to the second supply voltage.

24. The method of claim 22, wherein the programming voltage is greater than the second pass voltage the string precharge voltage and the source line pass voltage, the string precharge voltage is at least the source line pass voltage, and the first pass voltage is at least 0V.

25. The method of claim 24, wherein the string precharge voltage and the source line pass voltage are at the first pass voltage.

26. The method of claim 24, wherein the first pass voltage is greater than a programmed memory cell threshold voltage.

27. The method of claim 24, wherein the memory cells in advance of the selected memory cell in a sequential programming direction correspond to erased pages.

28. The method of claim 27, wherein the sequential programming direction includes a first direction being from the selected memory cell to the source line, and a second direction being from the selected memory cell to the bitline.

29. The method of claim 28, wherein the first pass voltage is set to 0V in the second programming direction.

30. A flash memory device comprising:

a driver for driving a source line select device, memory cells and a string select device connected in series between a bitline and a source line; and

a controller for controlling the driver in a programming operation, the controller being configured to

drive all wordlines of the memory cells to a first pass voltage for coupling a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage,

continue driving all the wordlines except a first wordline corresponding to a first memory cell adjacent to the a selected memory cell to second pass voltage greater than the first pass voltage, the first memory cell being positioned between the selected memory cell and the string select device,

drive a second wordline corresponding to a second memory cell adjacent to the selected memory cell to a first supply voltage for turning off the second memory cell,

drive a third wordline corresponding to the selected memory cell to a programming voltage greater than the second pass voltage, and

couple the bitline to the selected memory cell.

31. The flash memory device of claim 30, wherein the driver includes

wordline drivers for coupling row signals to the memory cells, a source select signal to the source line select device and a string select signal to a string select device,

a block decoder for enabling the wordline drivers in response to a block address, and,

a row decoder for providing the row signals, the source select signal and the string select signal in response to a row address.

32. The flash memory device of claim 31, wherein the row decoder includes a row decoder circuit for providing one of the row signals, the row decoder circuit including a multiplexor for selectively coupling one of the programming voltage, the first pass voltage and the second pass voltage to the one of the row signals.

33. The flash memory device of claim 32, wherein the row decoder includes a row decoder circuit for providing the source select signal, the row decoder circuit including a multiplexor for selectively coupling one of VSS and the second pass voltage to the source select signal.

34. The flash memory device of claim 32, wherein the row decoder includes a row decoder circuit for providing the string select signal, the row decoder circuit including a multiplexor for selectively coupling one of VSS and VDD to the string select signal.